From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 23:04:12 +0000 (-0700)
Subject: Make genvar a signed type
X-Git-Tag: yosys-0.9~57^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c27ab609faeeb3ae9372ea4cf85e5ac6ba029646;p=yosys.git

Make genvar a signed type
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 4895d0302..d89b2dc88 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -517,6 +517,7 @@ wire_type_token:
 	TOK_GENVAR {
 		astbuf3->type = AST_GENVAR;
 		astbuf3->is_reg = true;
+		astbuf3->is_signed = true;
 		astbuf3->range_left = 31;
 		astbuf3->range_right = 0;
 	} |