From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Jun 2020 15:36:58 +0000 (+0100)
Subject: use name of unit to write simulator/vcd file
X-Git-Tag: div_pipeline~531
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c29d74ff3526ef46febd0fe457f6d458a8a4a3ac;p=soc.git

use name of unit to write simulator/vcd file
---

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 425d1f92..d8233402 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -199,7 +199,10 @@ class TestRunner(FHDLTestCase):
                                                             sim, code)
 
         sim.add_sync_process(process)
-        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+
+        name = self.funit.name.lower()
+        with sim.write_vcd("%s_simulator.vcd" % name,
+                           "%s_simulator.gtkw" % name,
                             traces=[]):
             sim.run()