From: Luke Kenneth Casson Leighton Date: Wed, 10 Jun 2020 12:54:24 +0000 (+0100) Subject: continue ALUHelpers check alu outputs code-morph X-Git-Tag: div_pipeline~429 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2b3b419365e8fb9bd2237632819f371c967b0c1;p=soc.git continue ALUHelpers check alu outputs code-morph --- diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index c6378859..ee99518a 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -266,13 +266,6 @@ class TestRunner(FHDLTestCase): sim.run() def check_alu_outputs(self, alu, dec2, sim, code): - sim_o = {} - res = {} - - # check RT - yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) - yield from ALUHelpers.get_int_o(res, alu, dec2) - ALUHelpers.check_int_o(self, res, sim_o, code) rc = yield dec2.e.rc.data cridx_ok = yield dec2.e.write_cr.ok @@ -282,39 +275,35 @@ class TestRunner(FHDLTestCase): if rc: self.assertEqual(cridx, 0, code) - yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2) - yield from ALUHelpers.get_cr_a(res, alu, dec2) - ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) - - cry_out = yield dec2.e.output_carry - if cry_out: - expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 - real_carry = yield alu.n.data_o.xer_ca.data[0] # XXX CA not CA32 - self.assertEqual(expected_carry, real_carry, code) - expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0 - real_carry32 = yield alu.n.data_o.xer_ca.data[1] # XXX CA32 - self.assertEqual(expected_carry32, real_carry32, code) - oe = yield dec2.e.oe.oe oe_ok = yield dec2.e.oe.ok - if oe and oe_ok: - expected_so = 1 if sim.spr['XER'][XER_bits['SO']] else 0 - real_so = yield alu.n.data_o.xer_so.data[0] - self.assertEqual(expected_so, real_so, code) - expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0 - real_ov = yield alu.n.data_o.xer_ov.data[0] # OV bit - self.assertEqual(expected_ov, real_ov, code) - expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0 - real_ov32 = yield alu.n.data_o.xer_ov.data[1] # OV32 bit - self.assertEqual(expected_ov32, real_ov32, code) - print ("after: so/ov/32", real_so, real_ov, real_ov32) - else: + if not oe or not oe_ok: # if OE not enabled, XER SO and OV must correspondingly be false so_ok = yield alu.n.data_o.xer_so.ok ov_ok = yield alu.n.data_o.xer_ov.ok self.assertEqual(so_ok, False, code) self.assertEqual(ov_ok, False, code) + sim_o = {} + res = {} + + yield from ALUHelpers.get_cr_a(res, alu, dec2) + yield from ALUHelpers.get_xer_ov(res, alu, dec2) + yield from ALUHelpers.get_xer_ca(res, alu, dec2) + yield from ALUHelpers.get_int_o(res, alu, dec2) + yield from ALUHelpers.get_xer_so(res, alu, dec2) + + yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) + yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2) + yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) + yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2) + yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) + + ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) + ALUHelpers.check_xer_ov(self, res, sim_o, code) + ALUHelpers.check_xer_ca(self, res, sim_o, code) + ALUHelpers.check_int_o(self, res, sim_o, code) + ALUHelpers.check_xer_so(self, res, sim_o, code) if __name__ == "__main__": diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index 997f022b..5ae88187 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -1,3 +1,6 @@ +from soc.decoder.power_enums import XER_bits + + class TestCase: def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None, msr=0): @@ -92,6 +95,23 @@ class ALUHelpers: if cridx_ok: res['cr_a'] = yield alu.n.data_o.cr0.data + def get_xer_so(res, alu, dec2): + oe = yield dec2.e.oe.oe + oe_ok = yield dec2.e.oe.ok + if oe and oe_ok: + res['xer_so'] = yield alu.n.data_o.xer_so.data[0] + + def get_xer_ov(res, alu, dec2): + oe = yield dec2.e.oe.oe + oe_ok = yield dec2.e.oe.ok + if oe and oe_ok: + res['xer_ov'] = yield alu.n.data_o.xer_ov.data + + def get_xer_ca(res, alu, dec2): + cry_out = yield dec2.e.output_carry + if cry_out: + res['xer_ca'] = yield alu.n.data_o.xer_ca.data + def get_sim_int_o(res, sim, dec2): out_reg_valid = yield dec2.e.write_reg.ok if out_reg_valid: @@ -104,6 +124,27 @@ class ALUHelpers: cridx = yield dec2.e.write_cr.data res['cr_a'] = sim.crl[cridx].get_range().value + def get_sim_xer_ca(res, sim, dec2): + cry_out = yield dec2.e.output_carry + if cry_out: + expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 + expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0 + res['xer_ca'] = expected_carry | (expected_carry32 << 1) + + def get_sim_xer_ov(res, sim, dec2): + oe = yield dec2.e.oe.oe + oe_ok = yield dec2.e.oe.ok + if oe and oe_ok: + expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0 + expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0 + res['xer_ov'] = expected_ov | (expected_ov32 << 1) + + def get_sim_xer_so(res, sim, dec2): + oe = yield dec2.e.oe.oe + oe_ok = yield dec2.e.oe.ok + if oe and oe_ok: + res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0 + def check_int_o(dut, res, sim_o, msg): if 'o' in res: expected = sim_o['o'] @@ -118,3 +159,24 @@ class ALUHelpers: print ("CR", cr_expected, cr_actual) dut.assertEqual(cr_expected, cr_actual, msg) + def check_xer_ca(dut, res, sim_o, msg): + if 'xer_ca' in res: + ca_expected = sim_o['xer_ca'] + ca_actual = res['xer_ca'] + print ("CA", ca_expected, ca_actual) + dut.assertEqual(ca_expected, ca_actual, msg) + + def check_xer_ov(dut, res, sim_o, msg): + if 'xer_ov' in res: + ov_expected = sim_o['xer_ov'] + ov_actual = res['xer_ov'] + print ("OV", ov_expected, ov_actual) + dut.assertEqual(ov_expected, ov_actual, msg) + + def check_xer_so(dut, res, sim_o, msg): + if 'xer_so' in res: + so_expected = sim_o['xer_so'] + so_actual = res['xer_so'] + print ("SO", so_expected, so_actual) + dut.assertEqual(so_expected, so_actual, msg) +