From: Marcin Kościelnicki <mwk@0x04.net>
Date: Mon, 23 Mar 2020 10:07:03 +0000 (+0100)
Subject: techmap: Fix cell names with _TECHMAP_REPLACE_.*
X-Git-Tag: working-ls180~728^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2bf11e42a6de3f028ad0b484eb24b70618c6fc7;p=yosys.git

techmap: Fix cell names with _TECHMAP_REPLACE_.*

Fixes #1804.
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 0c57733d4..10001baaa 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -177,10 +177,10 @@ struct TechmapWorker
 		std::string orig_cell_name;
 		pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
 
+		orig_cell_name = cell->name.str();
 		if (!flatten_mode) {
 			for (auto &it : tpl->cells_)
 				if (it.first == ID(_TECHMAP_REPLACE_)) {
-					orig_cell_name = cell->name.str();
 					module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
 					break;
 				}
diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index c2f42d50b..8403586bd 100644
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -16,3 +16,21 @@ EOT
 techmap -map %techmap
 select -assert-any w:s0.asdf
 select -assert-any c:s0.blah
+
+read_verilog <<EOT
+module sub(input i, output o, input j);
+wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+select -assert-any w:s0.asdf
+select -assert-any c:s0.blah