From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 16 Feb 2019 07:35:51 +0000 (+0000)
Subject: no real point adding reset for internal pipeline variables
X-Git-Tag: ls180-24jan2020~1976
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2c01f96fcde637744e0490648f2f17956f82655;p=ieee754fpu.git

no real point adding reset for internal pipeline variables
---

diff --git a/src/add/pipeline.py b/src/add/pipeline.py
index bf35b6b3..6e5434af 100644
--- a/src/add/pipeline.py
+++ b/src/add/pipeline.py
@@ -45,7 +45,8 @@ class SimplePipeline(object):
             next_stage = self._current_stage_num + 1
             pipereg_id = str(self._current_stage_num) + 'to' + str(next_stage)
             rname = 'pipereg_' + pipereg_id + '_' + name
-            new_pipereg = Signal(value_bits_sign(value), name=rname)
+            new_pipereg = Signal(value_bits_sign(value), name=rname,
+                                 reset_less=True)
             if next_stage not in self._pipeline_register_map:
                 self._pipeline_register_map[next_stage] = {}
             self._pipeline_register_map[next_stage][name] = new_pipereg