From: Luke Kenneth Casson Leighton Date: Mon, 1 Oct 2018 01:16:02 +0000 (+0100) Subject: clarify that LR/SC are not to be parallelised X-Git-Tag: convert-csv-opcode-to-binary~5001 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2c2dd2f59caaa2fd5cd9ecf901f8473324b4d35;p=libreriscv.git clarify that LR/SC are not to be parallelised --- diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 9f0e3536b..5ca195208 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -331,7 +331,10 @@ instructions are added to any given RV extension, their functionality will be inherently parallelised. CSR instructions, LUI, C.J, C.JR, WFI, AUIPC are not suitable for parallelising -so are left as scalar. EBREAK, NOP, FENCE and others do not use registers +so are left as scalar. LR/SC could hypothetically be parallelised +however their purpose is single (complex) atomic memory operations, and +it would be unwise to attempt to parallelise them. +EBREAK, NOP, FENCE and others do not use registers so are not inherently paralleliseable either. All other operations using registers are automatically parallelised.