From: lkcl <lkcl@web>
Date: Sat, 6 May 2023 09:14:44 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2d5fcf73d660f86855e7de4e75dd8ad7f248a2b;p=libreriscv.git

---

diff --git a/openpower/sv/svstep.mdwn b/openpower/sv/svstep.mdwn
index 2581de6de..133a5daed 100644
--- a/openpower/sv/svstep.mdwn
+++ b/openpower/sv/svstep.mdwn
@@ -136,7 +136,7 @@ found in Vector ISAs.
 **Use of svstep with Vertical-First sub-vectors**
 
 Incrementing and iteration through subvector state ssubstep and dsubstep is
-possible with `sv.svstep/vecN` where N may be 2/3/4.  However it is necessary
+possible with `sv.svstep/vecN` where as expected N may be 2/3/4.  However it is necessary
 to use the exact same Sub-Vector qualifier on any Prefixed
 instructions, within any given Vertical-First loop. Also valid
 is not specifying a Sub-vector