From: Cesar Strauss <cestrauss@gmail.com>
Date: Tue, 9 Mar 2021 10:49:03 +0000 (-0300)
Subject: Create a new signal for the Simulator to wait on
X-Git-Tag: convert-csv-opcode-to-binary~81
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2ea3f4a716cd533206ade022d9227f56197fa0c;p=soc.git

Create a new signal for the Simulator to wait on

We wait on "core busy" before simulating an instruction. Trouble is, on a
VL==0 loop, there is no issue, so busy is never toggled. As a solution,
export a new insn_done signal with is pulsed either at end of Execute, or
when going back to Fetch due to skipping a vector instruction.
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 5aa8788e..e0bd3595 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -153,6 +153,9 @@ class TestIssuerInternal(Elaboratable):
         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
         self.state_nia.wen.name = 'state_nia_wen'
 
+        # pulse to synchronize the simulator at instruction end
+        self.insn_done = Signal()
+
     def fetch_fsm(self, m, core, pc, svstate, nia,
                         fetch_pc_ready_o, fetch_pc_valid_i,
                         fetch_insn_valid_o, fetch_insn_ready_i):
@@ -322,6 +325,7 @@ class TestIssuerInternal(Elaboratable):
                         # executed that we could be overwriting
                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
                         comb += self.state_w_pc.data_i.eq(nia)
+                        comb += self.insn_done.eq(1)
                         m.next = "INSN_FETCH"
                     with m.Else():
                         m.next = "INSN_EXECUTE"  # move to "execute"
@@ -448,6 +452,7 @@ class TestIssuerInternal(Elaboratable):
                 with m.If(~core_busy_o): # instruction done!
                     comb += exec_pc_valid_o.eq(1)
                     with m.If(exec_pc_ready_i):
+                        comb += self.insn_done.eq(1)
                         m.next = "INSN_START"  # back to fetch
 
     def elaborate(self, platform):
diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 9e06b8c2..957cd080 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -257,8 +257,12 @@ class TestRunner(FHDLTestCase):
                     counter = counter + 1
 
                     # wait until executed
-                    yield from wait_for_busy_hi(core)
-                    yield from wait_for_busy_clear(core)
+                    # wait for insn_done high
+                    while not (yield issuer.insn_done):
+                        yield
+                    # wait for insn_done low
+                    while (yield issuer.insn_done):
+                        yield
 
                     # set up simulated instruction (in simdec2)
                     try: