From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:06:12 +0000 (+0200) Subject: Moved all tests in arch sub directory X-Git-Tag: working-ls180~985^2~7 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1;p=yosys.git Moved all tests in arch sub directory --- diff --git a/Makefile b/Makefile index 70d683c34..a24f19b6a 100644 --- a/Makefile +++ b/Makefile @@ -713,12 +713,12 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/opt && bash run-test.sh +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh - +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/xilinx && bash run-test.sh $(SEEDOPT) + +cd tests/arch/ecp5 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/efinix && bash run-test.sh $(SEEDOPT) + +cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh - +cd tests/efinix && bash run-test.sh $(SEEDOPT) - +cd tests/anlogic && bash run-test.sh $(SEEDOPT) - +cd tests/ecp5 && bash run-test.sh $(SEEDOPT) - +cd tests/xilinx && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/anlogic/.gitignore b/tests/anlogic/.gitignore deleted file mode 100644 index 9a71dca69..000000000 --- a/tests/anlogic/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*.log -/run-test.mk -+*_synth.v -+*_testbench diff --git a/tests/anlogic/add_sub.v b/tests/anlogic/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/anlogic/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys deleted file mode 100644 index b8b67cc46..000000000 --- a/tests/anlogic/add_sub.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:AL_MAP_ADDER -select -assert-count 4 t:AL_MAP_LUT1 - -select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/counter.v b/tests/anlogic/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/anlogic/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/anlogic/counter.ys b/tests/anlogic/counter.ys deleted file mode 100644 index 036fdba46..000000000 --- a/tests/anlogic/counter.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog counter.v -hierarchy -top top -proc -flatten -equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 9 t:AL_MAP_ADDER -select -assert-count 8 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/dffs.v b/tests/anlogic/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/anlogic/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys deleted file mode 100644 index 9cbe5fce7..000000000 --- a/tests/anlogic/dffs.ys +++ /dev/null @@ -1,20 +0,0 @@ -read_verilog dffs.v -design -save read - -hierarchy -top dff -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dff # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_SEQ %% t:* %D - -design -load read -hierarchy -top dffe -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffe # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 -select -assert-count 1 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/anlogic/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys deleted file mode 100644 index 452ef9251..000000000 --- a/tests/anlogic/fsm.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog fsm.v -hierarchy -top fsm -proc -#flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd fsm # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT2 -select -assert-count 5 t:AL_MAP_LUT5 -select -assert-count 1 t:AL_MAP_LUT6 -select -assert-count 6 t:AL_MAP_SEQ - -select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/latches.v b/tests/anlogic/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/anlogic/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys deleted file mode 100644 index c00c7a25d..000000000 --- a/tests/anlogic/latches.ys +++ /dev/null @@ -1,33 +0,0 @@ -read_verilog latches.v -design -save read - -hierarchy -top latchp -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic -cd latchp # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 - -select -assert-none t:AL_MAP_LUT3 %% t:* %D - - -design -load read -hierarchy -top latchn -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic -cd latchn # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 - -select -assert-none t:AL_MAP_LUT3 %% t:* %D - - -design -load read -hierarchy -top latchsr -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic -cd latchsr # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT5 - -select -assert-none t:AL_MAP_LUT5 %% t:* %D diff --git a/tests/anlogic/memory.v b/tests/anlogic/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/anlogic/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/anlogic/memory.ys b/tests/anlogic/memory.ys deleted file mode 100644 index 8c0ce844e..000000000 --- a/tests/anlogic/memory.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. -#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top - -select -assert-count 8 t:AL_MAP_LUT2 -select -assert-count 8 t:AL_MAP_LUT4 -select -assert-count 8 t:AL_MAP_LUT5 -select -assert-count 36 t:AL_MAP_SEQ -select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? -select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/anlogic/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys deleted file mode 100644 index 64ed2a2bd..000000000 --- a/tests/anlogic/mux.ys +++ /dev/null @@ -1,42 +0,0 @@ -read_verilog mux.v -design -save read - -hierarchy -top mux2 -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux2 # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 - -select -assert-none t:AL_MAP_LUT3 %% t:* %D - -design -load read -hierarchy -top mux4 -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux4 # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT6 - -select -assert-none t:AL_MAP_LUT6 %% t:* %D - -design -load read -hierarchy -top mux8 -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux8 # Constrain all select calls below inside the top module -select -assert-count 3 t:AL_MAP_LUT4 -select -assert-count 1 t:AL_MAP_LUT6 - -select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D - -design -load read -hierarchy -top mux16 -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux16 # Constrain all select calls below inside the top module -select -assert-count 5 t:AL_MAP_LUT6 - -select -assert-none t:AL_MAP_LUT6 %% t:* %D diff --git a/tests/anlogic/run-test.sh b/tests/anlogic/run-test.sh deleted file mode 100755 index 46716f9a0..000000000 --- a/tests/anlogic/run-test.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env bash -set -e -{ -echo "all::" -for x in *.ys; do - echo "all:: run-$x" - echo "run-$x:" - echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" -done -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done -} > run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/anlogic/shifter.v b/tests/anlogic/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/anlogic/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/anlogic/shifter.ys b/tests/anlogic/shifter.ys deleted file mode 100644 index 5eaed30a3..000000000 --- a/tests/anlogic/shifter.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog shifter.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 8 t:AL_MAP_SEQ - -select -assert-none t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v deleted file mode 100644 index 90dd314e4..000000000 --- a/tests/anlogic/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule diff --git a/tests/anlogic/tribuf.ys b/tests/anlogic/tribuf.ys deleted file mode 100644 index 0eb1338ac..000000000 --- a/tests/anlogic/tribuf.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog tribuf.v -hierarchy -top tristate -proc -flatten -equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristate # Constrain all select calls below inside the top module -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/anlogic/.gitignore b/tests/arch/anlogic/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/arch/anlogic/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/arch/anlogic/add_sub.v b/tests/arch/anlogic/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/arch/anlogic/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/arch/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys new file mode 100644 index 000000000..b8b67cc46 --- /dev/null +++ b/tests/arch/anlogic/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:AL_MAP_ADDER +select -assert-count 4 t:AL_MAP_LUT1 + +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D diff --git a/tests/arch/anlogic/counter.v b/tests/arch/anlogic/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/anlogic/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys new file mode 100644 index 000000000..036fdba46 --- /dev/null +++ b/tests/arch/anlogic/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:AL_MAP_ADDER +select -assert-count 8 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/arch/anlogic/dffs.v b/tests/arch/anlogic/dffs.v new file mode 100644 index 000000000..3418787c9 --- /dev/null +++ b/tests/arch/anlogic/dffs.v @@ -0,0 +1,15 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule diff --git a/tests/arch/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys new file mode 100644 index 000000000..9cbe5fce7 --- /dev/null +++ b/tests/arch/anlogic/dffs.ys @@ -0,0 +1,20 @@ +read_verilog dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/arch/anlogic/fsm.v b/tests/arch/anlogic/fsm.v new file mode 100644 index 000000000..368fbaace --- /dev/null +++ b/tests/arch/anlogic/fsm.v @@ -0,0 +1,55 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + +endmodule diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys new file mode 100644 index 000000000..452ef9251 --- /dev/null +++ b/tests/arch/anlogic/fsm.ys @@ -0,0 +1,15 @@ +read_verilog fsm.v +hierarchy -top fsm +proc +#flatten +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT2 +select -assert-count 5 t:AL_MAP_LUT5 +select -assert-count 1 t:AL_MAP_LUT6 +select -assert-count 6 t:AL_MAP_SEQ + +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/arch/anlogic/latches.v b/tests/arch/anlogic/latches.v new file mode 100644 index 000000000..adb5d5319 --- /dev/null +++ b/tests/arch/anlogic/latches.v @@ -0,0 +1,24 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule diff --git a/tests/arch/anlogic/latches.ys b/tests/arch/anlogic/latches.ys new file mode 100644 index 000000000..c00c7a25d --- /dev/null +++ b/tests/arch/anlogic/latches.ys @@ -0,0 +1,33 @@ +read_verilog latches.v +design -save read + +hierarchy -top latchp +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_anlogic +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_anlogic +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + + +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_anlogic +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT5 + +select -assert-none t:AL_MAP_LUT5 %% t:* %D diff --git a/tests/arch/anlogic/memory.v b/tests/arch/anlogic/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/arch/anlogic/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys new file mode 100644 index 000000000..8c0ce844e --- /dev/null +++ b/tests/arch/anlogic/memory.ys @@ -0,0 +1,21 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top + +select -assert-count 8 t:AL_MAP_LUT2 +select -assert-count 8 t:AL_MAP_LUT4 +select -assert-count 8 t:AL_MAP_LUT5 +select -assert-count 36 t:AL_MAP_SEQ +select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D diff --git a/tests/arch/anlogic/mux.v b/tests/arch/anlogic/mux.v new file mode 100644 index 000000000..27bc0bf0b --- /dev/null +++ b/tests/arch/anlogic/mux.v @@ -0,0 +1,65 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys new file mode 100644 index 000000000..64ed2a2bd --- /dev/null +++ b/tests/arch/anlogic/mux.ys @@ -0,0 +1,42 @@ +read_verilog mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT6 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 3 t:AL_MAP_LUT4 +select -assert-count 1 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 5 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT6 %% t:* %D diff --git a/tests/arch/anlogic/run-test.sh b/tests/arch/anlogic/run-test.sh new file mode 100755 index 000000000..46716f9a0 --- /dev/null +++ b/tests/arch/anlogic/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/anlogic/shifter.v b/tests/arch/anlogic/shifter.v new file mode 100644 index 000000000..04ae49d83 --- /dev/null +++ b/tests/arch/anlogic/shifter.v @@ -0,0 +1,16 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end + +endmodule diff --git a/tests/arch/anlogic/shifter.ys b/tests/arch/anlogic/shifter.ys new file mode 100644 index 000000000..5eaed30a3 --- /dev/null +++ b/tests/arch/anlogic/shifter.ys @@ -0,0 +1,10 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:AL_MAP_SEQ + +select -assert-none t:AL_MAP_SEQ %% t:* %D diff --git a/tests/arch/anlogic/tribuf.v b/tests/arch/anlogic/tribuf.v new file mode 100644 index 000000000..90dd314e4 --- /dev/null +++ b/tests/arch/anlogic/tribuf.v @@ -0,0 +1,8 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule diff --git a/tests/arch/anlogic/tribuf.ys b/tests/arch/anlogic/tribuf.ys new file mode 100644 index 000000000..0eb1338ac --- /dev/null +++ b/tests/arch/anlogic/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top tristate +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/ecp5/.gitignore b/tests/arch/ecp5/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/arch/ecp5/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/arch/ecp5/add_sub.v b/tests/arch/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/arch/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/arch/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys new file mode 100644 index 000000000..ee72d732f --- /dev/null +++ b/tests/arch/ecp5/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/arch/ecp5/adffs.v b/tests/arch/ecp5/adffs.v new file mode 100644 index 000000000..223b52d21 --- /dev/null +++ b/tests/arch/ecp5/adffs.v @@ -0,0 +1,47 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffs + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule diff --git a/tests/arch/ecp5/adffs.ys b/tests/arch/ecp5/adffs.ys new file mode 100644 index 000000000..c6780e565 --- /dev/null +++ b/tests/arch/ecp5/adffs.ys @@ -0,0 +1,40 @@ +read_verilog adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/arch/ecp5/counter.v b/tests/arch/ecp5/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/ecp5/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys new file mode 100644 index 000000000..8ef70778f --- /dev/null +++ b/tests/arch/ecp5/counter.ys @@ -0,0 +1,10 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:CCU2C +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/ecp5/dffs.v b/tests/arch/ecp5/dffs.v new file mode 100644 index 000000000..3418787c9 --- /dev/null +++ b/tests/arch/ecp5/dffs.v @@ -0,0 +1,15 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule diff --git a/tests/arch/ecp5/dffs.ys b/tests/arch/ecp5/dffs.ys new file mode 100644 index 000000000..a4f45d2fb --- /dev/null +++ b/tests/arch/ecp5/dffs.ys @@ -0,0 +1,19 @@ +read_verilog dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D \ No newline at end of file diff --git a/tests/arch/ecp5/dpram.v b/tests/arch/ecp5/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/arch/ecp5/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/ecp5/shifter.v b/tests/arch/ecp5/shifter.v new file mode 100644 index 000000000..04ae49d83 --- /dev/null +++ b/tests/arch/ecp5/shifter.v @@ -0,0 +1,16 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end + +endmodule diff --git a/tests/arch/ecp5/shifter.ys b/tests/arch/ecp5/shifter.ys new file mode 100644 index 000000000..e1901e1a8 --- /dev/null +++ b/tests/arch/ecp5/shifter.ys @@ -0,0 +1,10 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/ecp5/tribuf.v b/tests/arch/ecp5/tribuf.v new file mode 100644 index 000000000..90dd314e4 --- /dev/null +++ b/tests/arch/ecp5/tribuf.v @@ -0,0 +1,8 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule diff --git a/tests/arch/ecp5/tribuf.ys b/tests/arch/ecp5/tribuf.ys new file mode 100644 index 000000000..a6e9c9598 --- /dev/null +++ b/tests/arch/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top tristate +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/efinix/.gitignore b/tests/arch/efinix/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/arch/efinix/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk diff --git a/tests/arch/efinix/add_sub.v b/tests/arch/efinix/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/arch/efinix/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/arch/efinix/add_sub.ys b/tests/arch/efinix/add_sub.ys new file mode 100644 index 000000000..8bd28c68e --- /dev/null +++ b/tests/arch/efinix/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:EFX_ADD +select -assert-count 4 t:EFX_LUT4 +select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D + diff --git a/tests/arch/efinix/adffs.v b/tests/arch/efinix/adffs.v new file mode 100644 index 000000000..223b52d21 --- /dev/null +++ b/tests/arch/efinix/adffs.v @@ -0,0 +1,47 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffs + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule diff --git a/tests/arch/efinix/adffs.ys b/tests/arch/efinix/adffs.ys new file mode 100644 index 000000000..1069c6c5c --- /dev/null +++ b/tests/arch/efinix/adffs.ys @@ -0,0 +1,50 @@ +read_verilog adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE + +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D + + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE + +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D + + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D + + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/counter.v b/tests/arch/efinix/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/efinix/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/arch/efinix/counter.ys b/tests/arch/efinix/counter.ys new file mode 100644 index 000000000..82e61d39b --- /dev/null +++ b/tests/arch/efinix/counter.ys @@ -0,0 +1,12 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 8 t:EFX_FF +select -assert-count 9 t:EFX_ADD +select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_ADD %% t:* %D diff --git a/tests/arch/efinix/dffs.v b/tests/arch/efinix/dffs.v new file mode 100644 index 000000000..3418787c9 --- /dev/null +++ b/tests/arch/efinix/dffs.v @@ -0,0 +1,15 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule diff --git a/tests/arch/efinix/dffs.ys b/tests/arch/efinix/dffs.ys new file mode 100644 index 000000000..cdd288233 --- /dev/null +++ b/tests/arch/efinix/dffs.ys @@ -0,0 +1,24 @@ +read_verilog dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE + +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/fsm.v b/tests/arch/efinix/fsm.v new file mode 100644 index 000000000..368fbaace --- /dev/null +++ b/tests/arch/efinix/fsm.v @@ -0,0 +1,55 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + +endmodule diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys new file mode 100644 index 000000000..2ec75215d --- /dev/null +++ b/tests/arch/efinix/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top fsm +proc +flatten +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 6 t:EFX_FF +select -assert-count 15 t:EFX_LUT4 +select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/latches.v b/tests/arch/efinix/latches.v new file mode 100644 index 000000000..adb5d5319 --- /dev/null +++ b/tests/arch/efinix/latches.v @@ -0,0 +1,24 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule diff --git a/tests/arch/efinix/latches.ys b/tests/arch/efinix/latches.ys new file mode 100644 index 000000000..899d024ce --- /dev/null +++ b/tests/arch/efinix/latches.ys @@ -0,0 +1,33 @@ +read_verilog latches.v +design -save read + +hierarchy -top latchp +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_efinix +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_efinix +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_efinix +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/logic.v b/tests/arch/efinix/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/arch/efinix/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule diff --git a/tests/arch/efinix/logic.ys b/tests/arch/efinix/logic.ys new file mode 100644 index 000000000..fdedb337b --- /dev/null +++ b/tests/arch/efinix/logic.ys @@ -0,0 +1,9 @@ +read_verilog logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:EFX_LUT4 +select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/memory.v b/tests/arch/efinix/memory.v new file mode 100644 index 000000000..5634d6507 --- /dev/null +++ b/tests/arch/efinix/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [8:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/memory.ys new file mode 100644 index 000000000..fe24b0a9b --- /dev/null +++ b/tests/arch/efinix/memory.ys @@ -0,0 +1,18 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Called with -verify and proof did fail! +#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_RAM_5K +select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D diff --git a/tests/arch/efinix/mux.v b/tests/arch/efinix/mux.v new file mode 100644 index 000000000..27bc0bf0b --- /dev/null +++ b/tests/arch/efinix/mux.v @@ -0,0 +1,65 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys new file mode 100644 index 000000000..71a9681de --- /dev/null +++ b/tests/arch/efinix/mux.ys @@ -0,0 +1,41 @@ +read_verilog mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 2 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 5 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 12 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/run-test.sh b/tests/arch/efinix/run-test.sh new file mode 100755 index 000000000..46716f9a0 --- /dev/null +++ b/tests/arch/efinix/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/efinix/shifter.v b/tests/arch/efinix/shifter.v new file mode 100644 index 000000000..ce2c81dd2 --- /dev/null +++ b/tests/arch/efinix/shifter.v @@ -0,0 +1,16 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out << 1; + out[7] <= in; + end + +endmodule diff --git a/tests/arch/efinix/shifter.ys b/tests/arch/efinix/shifter.ys new file mode 100644 index 000000000..1a6b5565c --- /dev/null +++ b/tests/arch/efinix/shifter.ys @@ -0,0 +1,11 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 8 t:EFX_FF +select -assert-none t:EFX_GBUFCE t:EFX_FF %% t:* %D diff --git a/tests/arch/efinix/tribuf.v b/tests/arch/efinix/tribuf.v new file mode 100644 index 000000000..c64468253 --- /dev/null +++ b/tests/arch/efinix/tribuf.v @@ -0,0 +1,8 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; + + always @(en or i) + o <= (en)? i : 1'bZ; +endmodule diff --git a/tests/arch/efinix/tribuf.ys b/tests/arch/efinix/tribuf.ys new file mode 100644 index 000000000..2e2ab9e65 --- /dev/null +++ b/tests/arch/efinix/tribuf.ys @@ -0,0 +1,12 @@ +read_verilog tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +#Internal cell type used. Need support it. +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/ice40/.gitignore b/tests/arch/ice40/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/arch/ice40/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/arch/ice40/add_sub.v b/tests/arch/ice40/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/arch/ice40/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys new file mode 100644 index 000000000..4a998d98d --- /dev/null +++ b/tests/arch/ice40/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 +select -assert-count 6 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D + diff --git a/tests/arch/ice40/adffs.v b/tests/arch/ice40/adffs.v new file mode 100644 index 000000000..09dc36001 --- /dev/null +++ b/tests/arch/ice40/adffs.v @@ -0,0 +1,87 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffs + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre ) + if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre ) + if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffs u_dffs ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnr u_ndffnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/arch/ice40/adffs.ys b/tests/arch/ice40/adffs.ys new file mode 100644 index 000000000..548060b66 --- /dev/null +++ b/tests/arch/ice40/adffs.ys @@ -0,0 +1,11 @@ +read_verilog adffs.v +proc +flatten +equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFNS +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFS +select -assert-count 2 t:SB_LUT4 +select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/alu.v b/tests/arch/ice40/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/arch/ice40/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/arch/ice40/alu.ys b/tests/arch/ice40/alu.ys new file mode 100644 index 000000000..bd859efc4 --- /dev/null +++ b/tests/arch/ice40/alu.ys @@ -0,0 +1,11 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 62 t:SB_CARRY +select -assert-count 32 t:SB_DFF +select -assert-count 655 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/counter.v b/tests/arch/ice40/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/ice40/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys new file mode 100644 index 000000000..c65c21622 --- /dev/null +++ b/tests/arch/ice40/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:SB_CARRY +select -assert-count 8 t:SB_DFFR +select -assert-count 8 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/dffs.v b/tests/arch/ice40/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/arch/ice40/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/arch/ice40/dffs.ys b/tests/arch/ice40/dffs.ys new file mode 100644 index 000000000..ee7f884b1 --- /dev/null +++ b/tests/arch/ice40/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFF +select -assert-count 1 t:SB_DFFE +select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D diff --git a/tests/arch/ice40/div_mod.v b/tests/arch/ice40/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/arch/ice40/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/arch/ice40/div_mod.ys b/tests/arch/ice40/div_mod.ys new file mode 100644 index 000000000..821d6c301 --- /dev/null +++ b/tests/arch/ice40/div_mod.ys @@ -0,0 +1,9 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 59 t:SB_LUT4 +select -assert-count 41 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/arch/ice40/dpram.v b/tests/arch/ice40/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/arch/ice40/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/ice40/shifter.v b/tests/arch/ice40/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/arch/ice40/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/arch/ice40/shifter.ys b/tests/arch/ice40/shifter.ys new file mode 100644 index 000000000..47d95d298 --- /dev/null +++ b/tests/arch/ice40/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/arch/ice40/tribuf.v b/tests/arch/ice40/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/arch/ice40/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/arch/ice40/tribuf.ys b/tests/arch/ice40/tribuf.ys new file mode 100644 index 000000000..d1e1b3108 --- /dev/null +++ b/tests/arch/ice40/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys new file mode 100644 index 000000000..10c029e68 --- /dev/null +++ b/tests/arch/ice40/wrapcarry.ys @@ -0,0 +1,22 @@ +read_verilog <= 2**(SIZEOUT-1)) | overflow_reg; + +// Output accumulation result +assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out; + +endmodule diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys new file mode 100644 index 000000000..6e884b35a --- /dev/null +++ b/tests/arch/xilinx/macc.ys @@ -0,0 +1,31 @@ +read_verilog macc.v +design -save read + +hierarchy -top macc +proc +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd macc # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE +select -assert-count 1 t:DSP48E1 +select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D + +design -load read +hierarchy -top macc2 +proc +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd macc2 # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT2 +select -assert-count 41 t:LUT3 +select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/arch/xilinx/macc_tb.v b/tests/arch/xilinx/macc_tb.v new file mode 100644 index 000000000..64aed05c4 --- /dev/null +++ b/tests/arch/xilinx/macc_tb.v @@ -0,0 +1,96 @@ +`timescale 1ns / 1ps + +module testbench; + + parameter SIZEIN = 16, SIZEOUT = 40; + reg clk, ce, rst; + reg signed [SIZEIN-1:0] a, b; + output signed [SIZEOUT-1:0] REF_accum_out, accum_out; + output REF_overflow, overflow; + + integer errcount = 0; + + reg ERROR_FLAG = 0; + + task clkcycle; + begin + #5; + clk = ~clk; + #10; + clk = ~clk; + #2; + ERROR_FLAG = 0; + if (REF_accum_out !== accum_out) begin + $display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_overflow !== overflow) begin + $display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + #3; + end + endtask + + initial begin + //$dumpfile("test_macc.vcd"); + //$dumpvars(0, testbench); + + #2; + clk = 1'b0; + ce = 1'b0; + a = 0; + b = 0; + + rst = 1'b1; + repeat (10) begin + #10; + clk = 1'b1; + #10; + clk = 1'b0; + #10; + clk = 1'b1; + #10; + clk = 1'b0; + end + rst = 1'b0; + + repeat (10000) begin + clkcycle; + ce = 1; //$urandom & $urandom; + //rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; + a = $urandom & ~(1 << (SIZEIN-1)); + b = $urandom & ~(1 << (SIZEIN-1)); + end + + if (errcount == 0) begin + $display("All tests passed."); + $finish; + end else begin + $display("Caught %1d errors.", errcount); + $stop; + end + end + + macc2 ref ( + .clk(clk), + .ce(ce), + .rst(rst), + .a(a), + .b(b), + .accum_out(REF_accum_out), + .overflow(REF_overflow) + ); + + macc2_uut uut ( + .clk(clk), + .ce(ce), + .rst(rst), + .a(a), + .b(b), + .accum_out(accum_out), + .overflow(overflow) + ); +endmodule diff --git a/tests/arch/xilinx/memory.v b/tests/arch/xilinx/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/arch/xilinx/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys new file mode 100644 index 000000000..5402513a2 --- /dev/null +++ b/tests/arch/xilinx/memory.ys @@ -0,0 +1,17 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM64X1D +select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D diff --git a/tests/arch/xilinx/mul.v b/tests/arch/xilinx/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/arch/xilinx/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys new file mode 100644 index 000000000..66a06efdc --- /dev/null +++ b/tests/arch/xilinx/mul.ys @@ -0,0 +1,9 @@ +read_verilog mul.v +hierarchy -top top +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:DSP48E1 +select -assert-none t:DSP48E1 %% t:* %D diff --git a/tests/arch/xilinx/mul_unsigned.v b/tests/arch/xilinx/mul_unsigned.v new file mode 100644 index 000000000..e3713a642 --- /dev/null +++ b/tests/arch/xilinx/mul_unsigned.v @@ -0,0 +1,30 @@ +/* +Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89]. +*/ + +// Unsigned 16x24-bit Multiplier +// 1 latency stage on operands +// 3 latency stage after the multiplication +// File: multipliers2.v +// +module mul_unsigned (clk, A, B, RES); +parameter WIDTHA = /*16*/ 6; +parameter WIDTHB = /*24*/ 9; +input clk; +input [WIDTHA-1:0] A; +input [WIDTHB-1:0] B; +output [WIDTHA+WIDTHB-1:0] RES; +reg [WIDTHA-1:0] rA; +reg [WIDTHB-1:0] rB; +reg [WIDTHA+WIDTHB-1:0] M [3:0]; +integer i; +always @(posedge clk) + begin + rA <= A; + rB <= B; + M[0] <= rA * rB; + for (i = 0; i < 3; i = i+1) + M[i+1] <= M[i]; + end +assign RES = M[3]; +endmodule diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys new file mode 100644 index 000000000..62495b90c --- /dev/null +++ b/tests/arch/xilinx/mul_unsigned.ys @@ -0,0 +1,11 @@ +read_verilog mul_unsigned.v +hierarchy -top mul_unsigned +proc + +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-count 30 t:FDRE +select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D diff --git a/tests/arch/xilinx/mux.v b/tests/arch/xilinx/mux.v new file mode 100644 index 000000000..27bc0bf0b --- /dev/null +++ b/tests/arch/xilinx/mux.v @@ -0,0 +1,65 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys new file mode 100644 index 000000000..420dece4e --- /dev/null +++ b/tests/arch/xilinx/mux.ys @@ -0,0 +1,45 @@ +read_verilog mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 + +select -assert-none t:LUT3 %% t:* %D + + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D + + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT6 + +select -assert-none t:LUT3 t:LUT6 %% t:* %D + + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 5 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D diff --git a/tests/arch/xilinx/pmgen_xilinx_srl.ys b/tests/arch/xilinx/pmgen_xilinx_srl.ys new file mode 100644 index 000000000..ea2f20487 --- /dev/null +++ b/tests/arch/xilinx/pmgen_xilinx_srl.ys @@ -0,0 +1,57 @@ +read_verilog -icells < run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/xilinx/shifter.v b/tests/arch/xilinx/shifter.v new file mode 100644 index 000000000..04ae49d83 --- /dev/null +++ b/tests/arch/xilinx/shifter.v @@ -0,0 +1,16 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end + +endmodule diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys new file mode 100644 index 000000000..84e16f41e --- /dev/null +++ b/tests/arch/xilinx/shifter.ys @@ -0,0 +1,11 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/arch/xilinx/tribuf.v b/tests/arch/xilinx/tribuf.v new file mode 100644 index 000000000..c64468253 --- /dev/null +++ b/tests/arch/xilinx/tribuf.v @@ -0,0 +1,8 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; + + always @(en or i) + o <= (en)? i : 1'bZ; +endmodule diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys new file mode 100644 index 000000000..c9cfb8546 --- /dev/null +++ b/tests/arch/xilinx/tribuf.ys @@ -0,0 +1,12 @@ +read_verilog tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v new file mode 100644 index 000000000..bc2a15ab2 --- /dev/null +++ b/tests/arch/xilinx/xilinx_srl.v @@ -0,0 +1,40 @@ +module xilinx_srl_static_test(input i, clk, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[3], shift1[3]}; +endmodule + +module xilinx_srl_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[l2], shift1[l1]}; +endmodule + +module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); +parameter CLKPOL = 1; +parameter ENPOL = 1; +parameter DEPTH = 1; +parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; +reg [DEPTH-1:0] r = INIT; +wire clk = C ^ CLKPOL; +always @(posedge C) + if (E) + r <= { r[DEPTH-2:0], D }; +assign Q = r[L]; +endmodule diff --git a/tests/arch/xilinx/xilinx_srl.ys b/tests/arch/xilinx/xilinx_srl.ys new file mode 100644 index 000000000..b8df0e55a --- /dev/null +++ b/tests/arch/xilinx/xilinx_srl.ys @@ -0,0 +1,67 @@ +read_verilog xilinx_srl.v +design -save read + +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_static_test +prep +design -save gold + +techmap +xilinx_srl -fixed +opt + +# stat +# show -width +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +dump gate +sat -verify -prove-asserts -show-ports -seq 5 miter + +#design -load gold +#stat + +#design -load gate +#stat + +########## + +design -load read +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_variable_test +prep +design -save gold + +xilinx_srl -variable +opt + +#stat +# show -width +# write_verilog -noexpr -norename +select -assert-count 1 t:$dff +select -assert-count 1 t:$dff r:WIDTH=1 %i +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +# design -load gold +# stat + +# design -load gate +# stat diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore deleted file mode 100644 index 1d329c933..000000000 --- a/tests/ecp5/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.log -/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/ecp5/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys deleted file mode 100644 index ee72d732f..000000000 --- a/tests/ecp5/add_sub.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -proc -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:LUT4 -select -assert-none t:LUT4 %% t:* %D - diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v deleted file mode 100644 index 223b52d21..000000000 --- a/tests/ecp5/adffs.v +++ /dev/null @@ -1,47 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys deleted file mode 100644 index c6780e565..000000000 --- a/tests/ecp5/adffs.ys +++ /dev/null @@ -1,40 +0,0 @@ -read_verilog adffs.v -design -save read - -hierarchy -top adff -proc -equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd adff # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-none t:TRELLIS_FF %% t:* %D - -design -load read -hierarchy -top adffn -proc -equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd adffn # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-count 1 t:LUT4 -select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D - -design -load read -hierarchy -top dffs -proc -equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffs # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-count 1 t:LUT4 -select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D - -design -load read -hierarchy -top ndffnr -proc -equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd ndffnr # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-count 1 t:LUT4 -select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/counter.v b/tests/ecp5/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/ecp5/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys deleted file mode 100644 index 8ef70778f..000000000 --- a/tests/ecp5/counter.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog counter.v -hierarchy -top top -proc -flatten -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 4 t:CCU2C -select -assert-count 8 t:TRELLIS_FF -select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/ecp5/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys deleted file mode 100644 index a4f45d2fb..000000000 --- a/tests/ecp5/dffs.ys +++ /dev/null @@ -1,19 +0,0 @@ -read_verilog dffs.v -design -save read - -hierarchy -top dff -proc -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dff # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-none t:TRELLIS_FF %% t:* %D - -design -load read -hierarchy -top dffe -proc -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffe # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-none t:TRELLIS_FF %% t:* %D \ No newline at end of file diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v deleted file mode 100644 index 3ea4c1f27..000000000 --- a/tests/ecp5/dpram.v +++ /dev/null @@ -1,23 +0,0 @@ -/* -Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. -*/ -module top (din, write_en, waddr, wclk, raddr, rclk, dout); -parameter addr_width = 8; -parameter data_width = 8; -input [addr_width-1:0] waddr, raddr; -input [data_width-1:0] din; -input write_en, wclk, rclk; -output [data_width-1:0] dout; -reg [data_width-1:0] dout; -reg [data_width-1:0] mem [(1< run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/ecp5/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys deleted file mode 100644 index e1901e1a8..000000000 --- a/tests/ecp5/shifter.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog shifter.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 8 t:TRELLIS_FF -select -assert-none t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v deleted file mode 100644 index 90dd314e4..000000000 --- a/tests/ecp5/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys deleted file mode 100644 index a6e9c9598..000000000 --- a/tests/ecp5/tribuf.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog tribuf.v -hierarchy -top tristate -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristate # Constrain all select calls below inside the top module -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/efinix/.gitignore b/tests/efinix/.gitignore deleted file mode 100644 index b48f808a1..000000000 --- a/tests/efinix/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/*.log -/*.out -/run-test.mk diff --git a/tests/efinix/add_sub.v b/tests/efinix/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/efinix/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/efinix/add_sub.ys b/tests/efinix/add_sub.ys deleted file mode 100644 index 8bd28c68e..000000000 --- a/tests/efinix/add_sub.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:EFX_ADD -select -assert-count 4 t:EFX_LUT4 -select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D - diff --git a/tests/efinix/adffs.v b/tests/efinix/adffs.v deleted file mode 100644 index 223b52d21..000000000 --- a/tests/efinix/adffs.v +++ /dev/null @@ -1,47 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys deleted file mode 100644 index 1069c6c5c..000000000 --- a/tests/efinix/adffs.ys +++ /dev/null @@ -1,50 +0,0 @@ -read_verilog adffs.v -design -save read - -hierarchy -top adff -proc -equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd adff # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE - -select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D - - -design -load read -hierarchy -top adffn -proc -equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd adffn # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE - -select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D - - -design -load read -hierarchy -top dffs -proc -equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffs # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D - - -design -load read -hierarchy -top ndffnr -proc -equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd ndffnr # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/counter.v b/tests/efinix/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/efinix/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/efinix/counter.ys b/tests/efinix/counter.ys deleted file mode 100644 index 82e61d39b..000000000 --- a/tests/efinix/counter.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog counter.v -hierarchy -top top -proc -flatten -equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 8 t:EFX_FF -select -assert-count 9 t:EFX_ADD -select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_ADD %% t:* %D diff --git a/tests/efinix/dffs.v b/tests/efinix/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/efinix/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/efinix/dffs.ys b/tests/efinix/dffs.ys deleted file mode 100644 index cdd288233..000000000 --- a/tests/efinix/dffs.ys +++ /dev/null @@ -1,24 +0,0 @@ -read_verilog dffs.v -design -save read - -hierarchy -top dff -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dff # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE - -select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D - -design -load read -hierarchy -top dffe -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffe # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/fsm.v b/tests/efinix/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/efinix/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/efinix/fsm.ys b/tests/efinix/fsm.ys deleted file mode 100644 index 2ec75215d..000000000 --- a/tests/efinix/fsm.ys +++ /dev/null @@ -1,14 +0,0 @@ -read_verilog fsm.v -hierarchy -top fsm -proc -flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd fsm # Constrain all select calls below inside the top module - -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 6 t:EFX_FF -select -assert-count 15 t:EFX_LUT4 -select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/latches.v b/tests/efinix/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/efinix/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/efinix/latches.ys b/tests/efinix/latches.ys deleted file mode 100644 index 899d024ce..000000000 --- a/tests/efinix/latches.ys +++ /dev/null @@ -1,33 +0,0 @@ -read_verilog latches.v -design -save read - -hierarchy -top latchp -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_efinix -cd latchp # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D - - -design -load read -hierarchy -top latchn -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_efinix -cd latchn # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D - - -design -load read -hierarchy -top latchsr -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_efinix -cd latchsr # Constrain all select calls below inside the top module -select -assert-count 2 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/logic.v b/tests/efinix/logic.v deleted file mode 100644 index e5343cae0..000000000 --- a/tests/efinix/logic.v +++ /dev/null @@ -1,18 +0,0 @@ -module top -( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - -endmodule diff --git a/tests/efinix/logic.ys b/tests/efinix/logic.ys deleted file mode 100644 index fdedb337b..000000000 --- a/tests/efinix/logic.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog logic.v -hierarchy -top top -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 9 t:EFX_LUT4 -select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/memory.v b/tests/efinix/memory.v deleted file mode 100644 index 5634d6507..000000000 --- a/tests/efinix/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [8:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/efinix/memory.ys b/tests/efinix/memory.ys deleted file mode 100644 index fe24b0a9b..000000000 --- a/tests/efinix/memory.ys +++ /dev/null @@ -1,18 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter -sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_RAM_5K -select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D diff --git a/tests/efinix/mux.v b/tests/efinix/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/efinix/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/efinix/mux.ys b/tests/efinix/mux.ys deleted file mode 100644 index 71a9681de..000000000 --- a/tests/efinix/mux.ys +++ /dev/null @@ -1,41 +0,0 @@ -read_verilog mux.v -design -save read - -hierarchy -top mux2 -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux2 # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D - -design -load read -hierarchy -top mux4 -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux4 # Constrain all select calls below inside the top module -select -assert-count 2 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D - -design -load read -hierarchy -top mux8 -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux8 # Constrain all select calls below inside the top module -select -assert-count 5 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D - -design -load read -hierarchy -top mux16 -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux16 # Constrain all select calls below inside the top module -select -assert-count 12 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/run-test.sh b/tests/efinix/run-test.sh deleted file mode 100755 index 46716f9a0..000000000 --- a/tests/efinix/run-test.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env bash -set -e -{ -echo "all::" -for x in *.ys; do - echo "all:: run-$x" - echo "run-$x:" - echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" -done -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done -} > run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/efinix/shifter.v b/tests/efinix/shifter.v deleted file mode 100644 index ce2c81dd2..000000000 --- a/tests/efinix/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out << 1; - out[7] <= in; - end - -endmodule diff --git a/tests/efinix/shifter.ys b/tests/efinix/shifter.ys deleted file mode 100644 index 1a6b5565c..000000000 --- a/tests/efinix/shifter.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog shifter.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 8 t:EFX_FF -select -assert-none t:EFX_GBUFCE t:EFX_FF %% t:* %D diff --git a/tests/efinix/tribuf.v b/tests/efinix/tribuf.v deleted file mode 100644 index c64468253..000000000 --- a/tests/efinix/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output reg o; - - always @(en or i) - o <= (en)? i : 1'bZ; -endmodule diff --git a/tests/efinix/tribuf.ys b/tests/efinix/tribuf.ys deleted file mode 100644 index 2e2ab9e65..000000000 --- a/tests/efinix/tribuf.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog tribuf.v -hierarchy -top tristate -proc -tribuf -flatten -synth -equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristate # Constrain all select calls below inside the top module -#Internal cell type used. Need support it. -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore deleted file mode 100644 index 9a71dca69..000000000 --- a/tests/ice40/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*.log -/run-test.mk -+*_synth.v -+*_testbench diff --git a/tests/ice40/add_sub.v b/tests/ice40/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/ice40/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys deleted file mode 100644 index 4a998d98d..000000000 --- a/tests/ice40/add_sub.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 11 t:SB_LUT4 -select -assert-count 6 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D - diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v deleted file mode 100644 index 09dc36001..000000000 --- a/tests/ice40/adffs.v +++ /dev/null @@ -1,87 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre ) - if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys deleted file mode 100644 index 548060b66..000000000 --- a/tests/ice40/adffs.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog adffs.v -proc -flatten -equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFFNS -select -assert-count 2 t:SB_DFFR -select -assert-count 1 t:SB_DFFS -select -assert-count 2 t:SB_LUT4 -select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/alu.v b/tests/ice40/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/ice40/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/ice40/alu.ys b/tests/ice40/alu.ys deleted file mode 100644 index bd859efc4..000000000 --- a/tests/ice40/alu.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_CARRY -select -assert-count 32 t:SB_DFF -select -assert-count 655 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/counter.v b/tests/ice40/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/ice40/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys deleted file mode 100644 index c65c21622..000000000 --- a/tests/ice40/counter.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog counter.v -hierarchy -top top -proc -flatten -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:SB_CARRY -select -assert-count 8 t:SB_DFFR -select -assert-count 8 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v deleted file mode 100644 index d97840c43..000000000 --- a/tests/ice40/dffs.v +++ /dev/null @@ -1,37 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys deleted file mode 100644 index ee7f884b1..000000000 --- a/tests/ice40/dffs.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog dffs.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFF -select -assert-count 1 t:SB_DFFE -select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D diff --git a/tests/ice40/div_mod.v b/tests/ice40/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/ice40/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys deleted file mode 100644 index 821d6c301..000000000 --- a/tests/ice40/div_mod.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 59 t:SB_LUT4 -select -assert-count 41 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/ice40/dpram.v b/tests/ice40/dpram.v deleted file mode 100644 index 3ea4c1f27..000000000 --- a/tests/ice40/dpram.v +++ /dev/null @@ -1,23 +0,0 @@ -/* -Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. -*/ -module top (din, write_en, waddr, wclk, raddr, rclk, dout); -parameter addr_width = 8; -parameter data_width = 8; -input [addr_width-1:0] waddr, raddr; -input [data_width-1:0] din; -input write_en, wclk, rclk; -output [data_width-1:0] dout; -reg [data_width-1:0] dout; -reg [data_width-1:0] mem [(1< run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ice40/shifter.v b/tests/ice40/shifter.v deleted file mode 100644 index c55632552..000000000 --- a/tests/ice40/shifter.v +++ /dev/null @@ -1,22 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin -`ifndef BUG - out <= out >> 1; - out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif - end - -endmodule diff --git a/tests/ice40/shifter.ys b/tests/ice40/shifter.ys deleted file mode 100644 index 47d95d298..000000000 --- a/tests/ice40/shifter.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog shifter.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 8 t:SB_DFF -select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/ice40/tribuf.v b/tests/ice40/tribuf.v deleted file mode 100644 index 870a02584..000000000 --- a/tests/ice40/tribuf.v +++ /dev/null @@ -1,23 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys deleted file mode 100644 index d1e1b3108..000000000 --- a/tests/ice40/tribuf.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog tribuf.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys deleted file mode 100644 index 10c029e68..000000000 --- a/tests/ice40/wrapcarry.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog <= 2**(SIZEOUT-1)) | overflow_reg; - -// Output accumulation result -assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out; - -endmodule diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys deleted file mode 100644 index 6e884b35a..000000000 --- a/tests/xilinx/macc.ys +++ /dev/null @@ -1,31 +0,0 @@ -read_verilog macc.v -design -save read - -hierarchy -top macc -proc -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd macc # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG -select -assert-count 1 t:FDRE -select -assert-count 1 t:DSP48E1 -select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D - -design -load read -hierarchy -top macc2 -proc -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd macc2 # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG -select -assert-count 1 t:DSP48E1 -select -assert-count 1 t:FDRE -select -assert-count 1 t:LUT2 -select -assert-count 41 t:LUT3 -select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/xilinx/macc_tb.v b/tests/xilinx/macc_tb.v deleted file mode 100644 index 64aed05c4..000000000 --- a/tests/xilinx/macc_tb.v +++ /dev/null @@ -1,96 +0,0 @@ -`timescale 1ns / 1ps - -module testbench; - - parameter SIZEIN = 16, SIZEOUT = 40; - reg clk, ce, rst; - reg signed [SIZEIN-1:0] a, b; - output signed [SIZEOUT-1:0] REF_accum_out, accum_out; - output REF_overflow, overflow; - - integer errcount = 0; - - reg ERROR_FLAG = 0; - - task clkcycle; - begin - #5; - clk = ~clk; - #10; - clk = ~clk; - #2; - ERROR_FLAG = 0; - if (REF_accum_out !== accum_out) begin - $display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out); - errcount = errcount + 1; - ERROR_FLAG = 1; - end - if (REF_overflow !== overflow) begin - $display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow); - errcount = errcount + 1; - ERROR_FLAG = 1; - end - #3; - end - endtask - - initial begin - //$dumpfile("test_macc.vcd"); - //$dumpvars(0, testbench); - - #2; - clk = 1'b0; - ce = 1'b0; - a = 0; - b = 0; - - rst = 1'b1; - repeat (10) begin - #10; - clk = 1'b1; - #10; - clk = 1'b0; - #10; - clk = 1'b1; - #10; - clk = 1'b0; - end - rst = 1'b0; - - repeat (10000) begin - clkcycle; - ce = 1; //$urandom & $urandom; - //rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; - a = $urandom & ~(1 << (SIZEIN-1)); - b = $urandom & ~(1 << (SIZEIN-1)); - end - - if (errcount == 0) begin - $display("All tests passed."); - $finish; - end else begin - $display("Caught %1d errors.", errcount); - $stop; - end - end - - macc2 ref ( - .clk(clk), - .ce(ce), - .rst(rst), - .a(a), - .b(b), - .accum_out(REF_accum_out), - .overflow(REF_overflow) - ); - - macc2_uut uut ( - .clk(clk), - .ce(ce), - .rst(rst), - .a(a), - .b(b), - .accum_out(accum_out), - .overflow(overflow) - ); -endmodule diff --git a/tests/xilinx/memory.v b/tests/xilinx/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/xilinx/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/xilinx/memory.ys b/tests/xilinx/memory.ys deleted file mode 100644 index 5402513a2..000000000 --- a/tests/xilinx/memory.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-count 8 t:RAM64X1D -select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D diff --git a/tests/xilinx/mul.v b/tests/xilinx/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/xilinx/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys deleted file mode 100644 index 66a06efdc..000000000 --- a/tests/xilinx/mul.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog mul.v -hierarchy -top top -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 1 t:DSP48E1 -select -assert-none t:DSP48E1 %% t:* %D diff --git a/tests/xilinx/mul_unsigned.v b/tests/xilinx/mul_unsigned.v deleted file mode 100644 index e3713a642..000000000 --- a/tests/xilinx/mul_unsigned.v +++ /dev/null @@ -1,30 +0,0 @@ -/* -Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89]. -*/ - -// Unsigned 16x24-bit Multiplier -// 1 latency stage on operands -// 3 latency stage after the multiplication -// File: multipliers2.v -// -module mul_unsigned (clk, A, B, RES); -parameter WIDTHA = /*16*/ 6; -parameter WIDTHB = /*24*/ 9; -input clk; -input [WIDTHA-1:0] A; -input [WIDTHB-1:0] B; -output [WIDTHA+WIDTHB-1:0] RES; -reg [WIDTHA-1:0] rA; -reg [WIDTHB-1:0] rB; -reg [WIDTHA+WIDTHB-1:0] M [3:0]; -integer i; -always @(posedge clk) - begin - rA <= A; - rB <= B; - M[0] <= rA * rB; - for (i = 0; i < 3; i = i+1) - M[i+1] <= M[i]; - end -assign RES = M[3]; -endmodule diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys deleted file mode 100644 index 62495b90c..000000000 --- a/tests/xilinx/mul_unsigned.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog mul_unsigned.v -hierarchy -top mul_unsigned -proc - -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mul_unsigned # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG -select -assert-count 1 t:DSP48E1 -select -assert-count 30 t:FDRE -select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/xilinx/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys deleted file mode 100644 index 420dece4e..000000000 --- a/tests/xilinx/mux.ys +++ /dev/null @@ -1,45 +0,0 @@ -read_verilog mux.v -design -save read - -hierarchy -top mux2 -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux2 # Constrain all select calls below inside the top module -select -assert-count 1 t:LUT3 - -select -assert-none t:LUT3 %% t:* %D - - -design -load read -hierarchy -top mux4 -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux4 # Constrain all select calls below inside the top module -select -assert-count 1 t:LUT6 - -select -assert-none t:LUT6 %% t:* %D - - -design -load read -hierarchy -top mux8 -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux8 # Constrain all select calls below inside the top module -select -assert-count 1 t:LUT3 -select -assert-count 2 t:LUT6 - -select -assert-none t:LUT3 t:LUT6 %% t:* %D - - -design -load read -hierarchy -top mux16 -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux16 # Constrain all select calls below inside the top module -select -assert-count 5 t:LUT6 - -select -assert-none t:LUT6 %% t:* %D diff --git a/tests/xilinx/pmgen_xilinx_srl.ys b/tests/xilinx/pmgen_xilinx_srl.ys deleted file mode 100644 index ea2f20487..000000000 --- a/tests/xilinx/pmgen_xilinx_srl.ys +++ /dev/null @@ -1,57 +0,0 @@ -read_verilog -icells < run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/xilinx/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/xilinx/shifter.ys b/tests/xilinx/shifter.ys deleted file mode 100644 index 84e16f41e..000000000 --- a/tests/xilinx/shifter.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog shifter.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v deleted file mode 100644 index c64468253..000000000 --- a/tests/xilinx/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output reg o; - - always @(en or i) - o <= (en)? i : 1'bZ; -endmodule diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys deleted file mode 100644 index c9cfb8546..000000000 --- a/tests/xilinx/tribuf.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog tribuf.v -hierarchy -top tristate -proc -tribuf -flatten -synth -equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristate # Constrain all select calls below inside the top module -# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx/xilinx_srl.v b/tests/xilinx/xilinx_srl.v deleted file mode 100644 index bc2a15ab2..000000000 --- a/tests/xilinx/xilinx_srl.v +++ /dev/null @@ -1,40 +0,0 @@ -module xilinx_srl_static_test(input i, clk, output [1:0] q); -reg head = 1'b0; -reg [3:0] shift1 = 4'b0000; -reg [3:0] shift2 = 4'b0000; - -always @(posedge clk) begin - head <= i; - shift1 <= {shift1[2:0], head}; - shift2 <= {shift2[2:0], head}; -end - -assign q = {shift2[3], shift1[3]}; -endmodule - -module xilinx_srl_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q); -reg head = 1'b0; -reg [3:0] shift1 = 4'b0000; -reg [3:0] shift2 = 4'b0000; - -always @(posedge clk) begin - head <= i; - shift1 <= {shift1[2:0], head}; - shift2 <= {shift2[2:0], head}; -end - -assign q = {shift2[l2], shift1[l1]}; -endmodule - -module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); -parameter CLKPOL = 1; -parameter ENPOL = 1; -parameter DEPTH = 1; -parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; -reg [DEPTH-1:0] r = INIT; -wire clk = C ^ CLKPOL; -always @(posedge C) - if (E) - r <= { r[DEPTH-2:0], D }; -assign Q = r[L]; -endmodule diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys deleted file mode 100644 index b8df0e55a..000000000 --- a/tests/xilinx/xilinx_srl.ys +++ /dev/null @@ -1,67 +0,0 @@ -read_verilog xilinx_srl.v -design -save read - -design -copy-to model $__XILINX_SHREG_ -hierarchy -top xilinx_srl_static_test -prep -design -save gold - -techmap -xilinx_srl -fixed -opt - -# stat -# show -width -select -assert-count 1 t:$_DFF_P_ -select -assert-count 2 t:$__XILINX_SHREG_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -dump gate -sat -verify -prove-asserts -show-ports -seq 5 miter - -#design -load gold -#stat - -#design -load gate -#stat - -########## - -design -load read -design -copy-to model $__XILINX_SHREG_ -hierarchy -top xilinx_srl_variable_test -prep -design -save gold - -xilinx_srl -variable -opt - -#stat -# show -width -# write_verilog -noexpr -norename -select -assert-count 1 t:$dff -select -assert-count 1 t:$dff r:WIDTH=1 %i -select -assert-count 2 t:$__XILINX_SHREG_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports -seq 5 miter - -# design -load gold -# stat - -# design -load gate -# stat