From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 26 Jul 2022 15:28:13 +0000 (+0100)
Subject: bit more docs on fmvis
X-Git-Tag: sv_maxu_works-initial~217
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c2f4debb657306be09d3221456e6bb23d4bbd00b;p=openpower-isa.git

bit more docs on fmvis
---

diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py
index fc3e56fc..f3f75530 100644
--- a/src/openpower/test/alu/fmvis_cases.py
+++ b/src/openpower/test/alu/fmvis_cases.py
@@ -13,14 +13,15 @@ import unittest
 class FMVISTestCase(TestAccumulatorBase):
 
     def case_0_fmvis(self):
-        lst = SVP64Asm(["fmvis 5, 0x4000",
+        lst = SVP64Asm(["fmvis 5, 0x4000", # 2.0
                         "fmvis 6, 0x2122",
-                        "fmvis 7, 0x3E80",
+                        "fmvis 7, 0x3E80", # 0.25
                        ])
         lst = list(lst)
 
         expected_fprs = [0] * 64
-        expected_fprs[5] = 0x4000000000000000
+        expected_fprs[5] = 0x4000000000000000 # 2.0 in FP64 form
         expected_fprs[6] = 0x2122000000000000
-        expected_fprs[7] = 0x3E80000000000000
-        self.add_case(Program(lst, bigendian), expected_fprs)
+        expected_fprs[7] = 0x3FD0000000000000 # 0.25 in FP64 form
+        e = ExpectedState(pc=4) # TODO, add FPRs
+        self.add_case(Program(lst, bigendian, e))