From: Luke Kenneth Casson Leighton Date: Thu, 2 Apr 2020 14:35:15 +0000 (+0100) Subject: add missing info X-Git-Tag: convert-csv-opcode-to-binary~2995 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c30ac68fb5d093c513c04280c695dc57562f5ba6;p=libreriscv.git add missing info --- diff --git a/openpower/isa/sprset.mdwn b/openpower/isa/sprset.mdwn index 1fd49b6d2..723ad2693 100644 --- a/openpower/isa/sprset.mdwn +++ b/openpower/isa/sprset.mdwn @@ -1,5 +1,7 @@ # Move To Special Purpose Register +XFX-Form + * mtspr SPR,RS n <- spr[5:9] || spr[0:4] @@ -12,8 +14,13 @@ else SPR(n) <- (RS) [32:63] +Special Registers Altered: + See spec 3.3.17 + # Move From Special Purpose Register +XFX-Form + * mfspr RT,SPR n <- spr[5:9] || spr[0:4] @@ -26,14 +33,24 @@ else RT <- [0]*32 || SPR(n) +Special Registers Altered: + None + # Move to CR from XER Extended +X-Form + * mcrxrx BF CR[4×BF+32:4×BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32] +Special Registers Altered: + CR field BF + # Move To One Condition Register Field +XFX-Form + * mtocrf FXM,RS count <- 0 @@ -45,15 +62,25 @@ CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35] else CR <- undefined +Special Registers Altered: + CR field selected by FXM + # Move To Condition Register Fields +XFX-Form + * mtcrf FXM,RS mask <- FXM[0]*4 || FXM[1]*4 || ... FXM[7]*4 CR <- ((RS)[32:63] & mask) | (CR & ¬mask) +Special Registers Altered: + CR fields selected by mask + # Move From One Condition Register Field +XFX-Form + * mfocrf RT,FXM RT <- undefined @@ -66,14 +93,24 @@ RT <- [0]*64 RT[4 *n+32:4*n+35] <- CR[4*n+32:4* n+35] +Special Registers Altered: + None + # Move From Condition Register +XFX-Form + * mfcr RT RT <- [0]*32 || CR +Special Registers Altered: + None + # Set Boolean +X-Form + * setb RT,BFA if CR[4×BFA+32] = 1 then @@ -83,3 +120,6 @@ else RT <- 0x0000_0000_0000_0000 +Special Registers Altered: + None +