From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 10 Jun 2019 23:16:26 +0000 (-0700)
Subject: Add test
X-Git-Tag: yosys-0.9~53^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c314ca3c51579a9c5305cbf9a69635e123db0423;p=yosys.git

Add test
---

diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
new file mode 100644
index 000000000..56e05c2c0
--- /dev/null
+++ b/tests/various/shregmap.v
@@ -0,0 +1,22 @@
+module shregmap_test(input i, clk, output [1:0] q);
+reg head = 1'b0;
+reg [3:0] shift1 = 4'b0000;
+reg [3:0] shift2 = 4'b0000;
+
+always @(posedge clk) begin
+    head <= i;
+    shift1 <= {shift1[2:0], head};
+    shift2 <= {shift2[2:0], head};
+end
+
+assign q = {shift2[3], shift1[3]};
+endmodule
+
+module $__SHREG_DFF_P_(input C, D, output Q);
+parameter DEPTH = 1;
+parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
+reg [DEPTH-1:0] r = INIT;
+always @(posedge C) 
+    r <= { r[DEPTH-2:0], D };
+assign Q = r[DEPTH-1];
+endmodule
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
new file mode 100644
index 000000000..ca7f47015
--- /dev/null
+++ b/tests/various/shregmap.ys
@@ -0,0 +1,31 @@
+read_verilog shregmap.v
+design -copy-to model $__SHREG_DFF_P_
+hierarchy -top shregmap_test
+prep
+design -save gold
+
+techmap
+shregmap -init
+
+opt
+
+stat
+# show -width
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 2 t:$__SHREG_DFF_P_
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
+prep
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 5 miter
+
+design -load gold
+stat
+
+design -load gate
+stat