From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 22 Mar 2023 21:42:27 +0000 (-0700)
Subject: partially fix FPCSR in "Special Registers altered" sections
X-Git-Tag: opf_rfc_ls001_v3~106
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3207e6ea70076278957eff0b61dcca3df89f881;p=libreriscv.git

partially fix FPCSR in "Special Registers altered" sections

didn't yet fill in "TODO: which bits?"
---

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index 026474a9e..50d0dccae 100644
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -271,7 +271,7 @@ operations.
 Special Registers altered:
 
     CR1     (if Rc=1)
-    FPCSR   (TODO: which bits?)
+    FPCSR   (TODO: which bits?) (if IT[0] != 0 or RCS[0] != 0)
 
 ### Assembly Aliases
 
@@ -574,6 +574,7 @@ Special Registers altered:
 
     CR0              (if Rc=1)
     XER SO, OV, OV32 (if OE=1)
+    FPCSR   (TODO: which bits?)
 
 ----------