From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 15 Aug 2019 19:34:11 +0000 (-0700)
Subject: xilinx_dsp to be sensitive to keep attribute
X-Git-Tag: working-ls180~1039^2~232
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c320abc3f490b09b21804581c2b386c30d186a1e;p=yosys.git

xilinx_dsp to be sensitive to keep attribute
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 1a3dcdcbb..7f1958d5d 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -29,8 +29,13 @@ match ffA
 endmatch
 
 code clock
-	if (ffA)
+	if (ffA) {
 		clock = port(ffA, \CLK).as_bit();
+
+		for (auto b : port(ffA, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
+	}
 endcode
 
 match ffB
@@ -45,6 +50,10 @@ endmatch
 
 code clock
 	if (ffB) {
+		for (auto b : port(ffB, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
+
 		SigBit c = port(ffB, \CLK).as_bit();
 
 		if (clock != SigBit() && c != clock)
@@ -156,6 +165,10 @@ code ffP clock
 //		ffP = ffY;
 
 	if (ffP) {
+		for (auto b : port(ffP, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
+
 		SigBit c = port(ffP, \CLK).as_bit();
 
 		if (clock != SigBit() && c != clock)