From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Dec 2019 16:59:17 +0000 (-0800)
Subject: Disable RAM16X1D match rule; carry-over from LUT4 arches
X-Git-Tag: working-ls180~921^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3262d60752bb20ff5cd54bc4ee6f56e2b772b05;p=yosys.git

Disable RAM16X1D match rule; carry-over from LUT4 arches
---

diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt
index be764a63f..ae629bce8 100644
--- a/techlibs/xilinx/lutrams.txt
+++ b/techlibs/xilinx/lutrams.txt
@@ -105,12 +105,15 @@ bram $__XILINX_RAM64M
 endbram
 
 
-match $__XILINX_RAM16X1D
-  min bits 2
-  min wports 1
-  make_outreg
-  or_next_if_better
-endmatch
+# Disabled for now, pending support for LUT4 arches
+#   since on LUT6 arches this occupies same area as
+#   a RAM32X1D
+#match $__XILINX_RAM16X1D
+#  min bits 2
+#  min wports 1
+#  make_outreg
+#  or_next_if_better
+#endmatch
 
 match $__XILINX_RAM32X1D
   min bits 3