From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 Jul 2020 15:05:23 +0000 (+0100)
Subject: re-enable div random tests and other regressions
X-Git-Tag: div_pipeline~106
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c32a8f7481da35803074d88d1492f6499e17c9ab;p=soc.git

re-enable div random tests and other regressions
---

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 663bb0ac..dd7d0153 100644
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -75,7 +75,7 @@ class DIVTestCase(FHDLTestCase):
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         self.test_data.append(tc)
 
-    def tst_0_regression(self):
+    def test_0_regression(self):
         for i in range(40):
             lst = ["divwo 3, 1, 2"]
             initial_regs = [0] * 32
@@ -83,35 +83,35 @@ class DIVTestCase(FHDLTestCase):
             initial_regs[2] = 0xcdf69a7f7042db66
             self.run_tst_program(Program(lst), initial_regs)
 
-    def tst_1_regression(self):
+    def test_1_regression(self):
         lst = ["divwo 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x10000000000000000-4
         initial_regs[2] = 0x10000000000000000-2
         self.run_tst_program(Program(lst), initial_regs)
 
-    def tst_2_regression(self):
+    def test_2_regression(self):
         lst = ["divwo 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xffffffffffff9321
         initial_regs[2] = 0xffffffffffff7012
         self.run_tst_program(Program(lst), initial_regs)
 
-    def tst_3_regression(self):
+    def test_3_regression(self):
         lst = ["divwo. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x1b8e32f2458746af
         initial_regs[2] = 0x6b8aee2ccf7d62e9
         self.run_tst_program(Program(lst), initial_regs)
 
-    def tst_4_regression(self):
+    def test_4_regression(self):
         lst = ["divw 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x1c4e6c2f3aa4a05c
         initial_regs[2] = 0xe730c2eed6cc8dd7
         self.run_tst_program(Program(lst), initial_regs)
 
-    def tst_5_regression(self):
+    def test_5_regression(self):
         lst = ["divw 3, 1, 2",
                "divwo. 6, 4, 5"]
         initial_regs = [0] * 32
@@ -140,7 +140,7 @@ class DIVTestCase(FHDLTestCase):
         initial_regs[2] = 0xffc868bf4573da0b
         self.run_tst_program(Program(lst), initial_regs)
 
-    def tst_rand_divw(self):
+    def test_rand_divw(self):
         insns = ["divw", "divw.", "divwo", "divwo."]
         for i in range(40):
             choice = random.choice(insns)
@@ -150,7 +150,7 @@ class DIVTestCase(FHDLTestCase):
             initial_regs[2] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)
 
-    def tst_ilang(self):
+    def test_ilang(self):
         pspec = DIVPipeSpec(id_wid=2)
         alu = DIVBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())