From: Antia Puentes Date: Thu, 25 Jan 2018 18:15:40 +0000 (+0100) Subject: intel: Handle firstvertex in an identical way to BaseVertex X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c32e1035cb4f1e0c2c1bd45611e3a35e7caf57b6;p=mesa.git intel: Handle firstvertex in an identical way to BaseVertex Until we set gl_BaseVertex to zero for non-indexed draw calls both have an identical value. The Vertex Elements are kept like that: * VE 1: * VE 2: v2 (idr): Mark nir_intrinsic_load_first_vertex as "unreachable" in emit_system_values_block and fs_visitor::nir_emit_vs_intrinsic. --- diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 6c4bcd1c113..a830bb9fcd6 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -116,6 +116,7 @@ emit_system_values_block(nir_block *block, fs_visitor *v) case nir_intrinsic_load_vertex_id_zero_base: case nir_intrinsic_load_base_vertex: + case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_instance_id: case nir_intrinsic_load_base_instance: case nir_intrinsic_load_draw_id: @@ -2458,6 +2459,9 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder &bld, break; } + case nir_intrinsic_load_first_vertex: + unreachable("lowered by brw_nir_lower_vs_inputs"); + default: nir_emit_intrinsic(bld, instr); break; diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 69ab162f888..16b0d86814f 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -239,6 +239,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir, const bool has_sgvs = nir->info.system_values_read & (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) | + BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) | BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) | BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) | BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID)); @@ -261,6 +262,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir, switch (intrin->intrinsic) { case nir_intrinsic_load_base_vertex: + case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_base_instance: case nir_intrinsic_load_vertex_id_zero_base: case nir_intrinsic_load_instance_id: @@ -278,6 +280,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir, nir_intrinsic_set_base(load, num_inputs); switch (intrin->intrinsic) { case nir_intrinsic_load_base_vertex: + case nir_intrinsic_load_first_vertex: nir_intrinsic_set_component(load, 0); break; case nir_intrinsic_load_base_instance: diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 9459d61af6c..1e384f5bf4d 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -2826,6 +2826,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, */ if (shader->info.system_values_read & (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) | + BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) | BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) | BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) | BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))) { diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 6d424019183..cd763645429 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -887,8 +887,12 @@ struct brw_context struct { struct { - /** The value of gl_BaseVertex for the current _mesa_prim. */ - int gl_basevertex; + /** + * Either the value of gl_BaseVertex for indexed draw calls or the + * value of the argument for non-indexed draw calls for the + * current _mesa_prim. + */ + int firstvertex; /** The value of gl_BaseInstance for the current _mesa_prim. */ int gl_baseinstance; diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 4caaadd560d..f51f083178e 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -819,25 +819,29 @@ brw_draw_single_prim(struct gl_context *ctx, * always flag if the shader uses one of the values. For direct draws, * we only flag if the values change. */ - const int new_basevertex = + const int new_firstvertex = prim->indexed ? prim->basevertex : prim->start; const int new_baseinstance = prim->base_instance; const struct brw_vs_prog_data *vs_prog_data = brw_vs_prog_data(brw->vs.base.prog_data); if (prim_id > 0) { - const bool uses_draw_parameters = + const bool uses_firstvertex = vs_prog_data->uses_basevertex || + vs_prog_data->uses_firstvertex; + + const bool uses_draw_parameters = + uses_firstvertex || vs_prog_data->uses_baseinstance; if ((uses_draw_parameters && prim->is_indirect) || - (vs_prog_data->uses_basevertex && - brw->draw.params.gl_basevertex != new_basevertex) || + (uses_firstvertex && + brw->draw.params.firstvertex != new_firstvertex) || (vs_prog_data->uses_baseinstance && brw->draw.params.gl_baseinstance != new_baseinstance)) brw->ctx.NewDriverState |= BRW_NEW_VERTICES; } - brw->draw.params.gl_basevertex = new_basevertex; + brw->draw.params.firstvertex = new_firstvertex; brw->draw.params.gl_baseinstance = new_baseinstance; brw_bo_unreference(brw->draw.draw_params_bo); diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 344e2f2b4ee..7573f780f23 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -704,8 +704,11 @@ brw_prepare_shader_draw_parameters(struct brw_context *brw) const struct brw_vs_prog_data *vs_prog_data = brw_vs_prog_data(brw->vs.base.prog_data); - /* For non-indirect draws, upload gl_BaseVertex. */ - if ((vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance) && + const bool uses_firstvertex = + vs_prog_data->uses_basevertex || vs_prog_data->uses_firstvertex; + + /* For non-indirect draws, upload the shader draw parameters */ + if ((uses_firstvertex || vs_prog_data->uses_baseinstance) && brw->draw.draw_params_bo == NULL) { brw_upload_data(&brw->upload, &brw->draw.params, sizeof(brw->draw.params), 4, diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index a69a496f1db..1a32c60ae34 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -539,7 +539,10 @@ genX(emit_vertices)(struct brw_context *brw) } #endif - const bool needs_sgvs_element = (vs_prog_data->uses_basevertex || + const bool uses_firstvertex = + vs_prog_data->uses_basevertex || vs_prog_data->uses_firstvertex; + + const bool needs_sgvs_element = (uses_firstvertex || vs_prog_data->uses_baseinstance || vs_prog_data->uses_instanceid || vs_prog_data->uses_vertexid); @@ -586,7 +589,7 @@ genX(emit_vertices)(struct brw_context *brw) /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */ const bool uses_draw_params = - vs_prog_data->uses_basevertex || + uses_firstvertex || vs_prog_data->uses_baseinstance; const unsigned nr_buffers = brw->vb.nr_buffers + uses_draw_params + vs_prog_data->uses_drawid; @@ -769,7 +772,7 @@ genX(emit_vertices)(struct brw_context *brw) }; #if GEN_GEN >= 8 - if (vs_prog_data->uses_basevertex || + if (uses_firstvertex || vs_prog_data->uses_baseinstance) { elem_state.VertexBufferIndex = brw->vb.nr_buffers; elem_state.SourceElementFormat = ISL_FORMAT_R32G32_UINT; @@ -779,7 +782,7 @@ genX(emit_vertices)(struct brw_context *brw) #else elem_state.VertexBufferIndex = brw->vb.nr_buffers; elem_state.SourceElementFormat = ISL_FORMAT_R32G32_UINT; - if (vs_prog_data->uses_basevertex) + if (uses_firstvertex) elem_state.Component0Control = VFCOMP_STORE_SRC; if (vs_prog_data->uses_baseinstance)