From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 24 Sep 2019 04:58:04 +0000 (-0700)
Subject: Force $inout.out ports to begin with '$' to indicate internal
X-Git-Tag: working-ls180~1039^2~31
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c340fbfab23c582103402bbd812d9bca4510dc41;p=yosys.git

Force $inout.out ports to begin with '$' to indicate internal
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index cbce4c83b..21b281708 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -424,7 +424,7 @@ struct XAigerWriter
 			// inherit existing inout's drivers
 			if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
 					|| keep_bits.count(bit)) {
-				RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
+				RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
 				RTLIL::Wire *new_wire = module->wire(wire_name);
 				if (!new_wire)
 					new_wire = module->addWire(wire_name, GetSize(wire));
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index e8ee487e5..986d34fb3 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -868,7 +868,7 @@ void AigerReader::post_process()
 					if (!existing) {
 						if (escaped_s.ends_with("$inout.out")) {
 							wire->port_output = false;
-							RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
+							RTLIL::Wire *in_wire = module->wire(escaped_s.substr(1, escaped_s.size()-11));
 							log_assert(in_wire);
 							log_assert(in_wire->port_input && !in_wire->port_output);
 							in_wire->port_output = true;
@@ -889,7 +889,7 @@ void AigerReader::post_process()
 					if (!existing) {
 						if (escaped_s.ends_with("$inout.out")) {
 							wire->port_output = false;
-							RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
+							RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(1, escaped_s.size()-11).c_str(), index));
 							log_assert(in_wire);
 							log_assert(in_wire->port_input && !in_wire->port_output);
 							in_wire->port_output = true;