From: lkcl <lkcl@web>
Date: Sun, 8 May 2022 19:47:21 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2298
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c34e3cb6214e468efb696cd75bfc2271c0380444;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 0acb474d5..20cd6a836 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -890,10 +890,13 @@ directly themselves.
 However the source code and binary would be near-identical if
 not identical in every respect, and the PEs implementing the full
 ZOLC capability in order to compact binary size to the bare minimum.
+The main CPU's role would be to coordinate and manage the PEs
+over OpenCAPI.
 
 One key strategic question does remain: do the PEs need to have
 a RADIX MMU and associated TLB-aware minimal L1 Cache, in order
-to support OpenCAPI properly? The saving grace here is that with
+to support OpenCAPI properly? The answer is very likely to be yes.
+The saving grace here is that with
 the expectation of running only hot-loops with ZOLC-driven
 binaries, the size of L1 Cache needed would be miniscule compared
 to the average high-end CPU.