From: lkcl <lkcl@web>
Date: Thu, 2 Jun 2022 11:38:12 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2015
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c35ad82c194c98fa02d44a1b91fc2e5177ac642e;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 90d689ca6..45e325dd7 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -11,7 +11,14 @@ SVP64 is designed around these fundamental and inviolate principles:
 3. A hardware-level for-loop makes vector elements 100% synonymous
    with scalar instructions (the suffix)
 
-That said, there are a few exceptional places where these rules get
+How can a Vector ISA even exist when no actual Vector instructions
+are permitted to be added? It comes down to the strict abstraction.
+First you add a **scalar** instruction (32-bit). Second, the
+Prefixing is applied *in the abstract* to give the *appearance*
+and ultimately the same effect as if an explicit Vector instruction
+had also been added.
+
+There are a few exceptional places where these rules get
 bent, and others where the rules take some explaining,
 and this page tracks them.