From: Sebastien Bourdeauducq Date: Tue, 29 Sep 2015 10:14:54 +0000 (+0800) Subject: command line options support, CSR CSV, all targets building X-Git-Tag: 24jan2021_ls180~2106^2~32 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c36029fa61524bbc5b09119cee296140b422e697;p=litex.git command line options support, CSR CSV, all targets building --- diff --git a/misoc/integration/builder.py b/misoc/integration/builder.py index e0ecce6e..e731ef50 100644 --- a/misoc/integration/builder.py +++ b/misoc/integration/builder.py @@ -5,6 +5,10 @@ import struct from misoc.integration import cpu_interface, sdram_init +__all__ = ["misoc_software_packages", "misoc_directory", + "Builder", "builder_args", "builder_argdict"] + + # in build order (for dependencies) misoc_software_packages = [ "libbase", @@ -20,11 +24,20 @@ misoc_directory = os.path.abspath(os.path.join(os.path.dirname(__file__), "..")) class Builder: - def __init__(self, soc, output_dir): + def __init__(self, soc, output_dir=None, + compile_software=True, compile_gateware=True, + csr_csv=None): self.soc = soc + if output_dir is None: + output_dir = "misoc_{}_{}".format( + soc.__class__.__name__.lower(), + soc.platform.name) # From Python doc: makedirs() will become confused if the path # elements to create include '..' self.output_dir = os.path.abspath(output_dir) + self.compile_software = compile_software + self.compile_gateware = compile_gateware + self.csr_csv = csr_csv self.software_packages = [] for name in misoc_software_packages: @@ -73,7 +86,11 @@ class Builder: with open(os.path.join(generated_dir, "sdram_phy.h"), "w") as f: f.write(sdram_init.get_sdram_phy_header(sdram_phy_settings)) - def _generate_software(self, compile): + if self.csr_csv is not None: + with open(self.csr_csv, "w") as f: + f.write(cpu_interface.get_csr_csv(csr_regions)) + + def _generate_software(self): for name, src_dir in self.software_packages: dst_dir = os.path.join(self.output_dir, "software", name) os.makedirs(dst_dir, exist_ok=True) @@ -84,7 +101,7 @@ class Builder: except FileNotFoundError: pass os.symlink(src, dst) - if compile: + if self.compile_software: subprocess.check_call(["make", "-C", dst_dir]) def _initialize_rom(self): @@ -100,15 +117,39 @@ class Builder: boot_data.append(struct.unpack(">I", w)[0]) self.soc.initialize_rom(boot_data) - def build(self, compile_software=True, compile_gateware=True): + def build(self): self.soc.finalize() - if self.soc.integrated_rom_size and not compile_software: + if self.soc.integrated_rom_size and not self.compile_software: raise ValueError("Software must be compiled in order to " "intitialize integrated ROM") self._generate_includes() - self._generate_software(compile_software) + self._generate_software() self._initialize_rom() self.soc.build(build_dir=os.path.join(self.output_dir, "gateware"), - run=compile_gateware) + run=self.compile_gateware) + + +def builder_args(parser): + parser.add_argument("--output-dir", default=None, + help="output directory for generated " + "source files and binaries") + parser.add_argument("--no-compile-software", action="store_true", + help="do not compile the software, only generate " + "build infrastructure") + parser.add_argument("--no-compile-gateware", action="store_true", + help="do not compile the gateware, only generate " + "HDL source files and build scripts") + parser.add_argument("--csr-csv", default=None, + help="store CSR map in CSV format into the " + "specified file") + + +def builder_argdict(args): + return { + "output_dir": args.output_dir, + "compile_software": not args.no_compile_software, + "compile_gateware": not args.no_compile_gateware, + "csr_csv": args.csr_csv + } diff --git a/misoc/integration/soc_core.py b/misoc/integration/soc_core.py index 3a92dbb8..cf8bbe56 100644 --- a/misoc/integration/soc_core.py +++ b/misoc/integration/soc_core.py @@ -6,6 +6,9 @@ from misoc.cores import lm32, mor1kx, identifier, timer, uart from misoc.interconnect import wishbone, csr_bus, wishbone2csr +__all__ = ["mem_decoder", "SoCCore", "soc_core_args", "soc_core_argdict"] + + def mem_decoder(address, start=26, end=29): return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1) @@ -190,3 +193,21 @@ class SoCCore(Module): def build(self, *args, **kwargs): self.platform.build(self, *args, **kwargs) + + +def soc_core_args(parser): + parser.add_argument("--cpu-type", default=None, + help="select CPU: lm32, or1k") + parser.add_argument("--integrated-rom-size", default=None, type=int, + help="size/enable the integrated (BIOS) ROM") + parser.add_argument("--integrated-main-ram-size", default=None, type=int, + help="size/enable the integrated main RAM") + + +def soc_core_argdict(args): + r = dict() + for a in "cpu_type", "integrated_rom_size", "integrated_main_ram_size": + arg = getattr(args, a) + if arg is not None: + r[a] = arg + return r diff --git a/misoc/integration/soc_sdram.py b/misoc/integration/soc_sdram.py index 64dac534..1bc813d5 100644 --- a/misoc/integration/soc_sdram.py +++ b/misoc/integration/soc_sdram.py @@ -4,13 +4,16 @@ from migen.genlib.record import * from misoc.interconnect import wishbone, wishbone2lasmi, lasmi_bus from misoc.interconnect.csr import AutoCSR from misoc.cores import sdram_tester, dfii, minicon, lasmicon -from misoc.integration.soc_core import SoCCore +from misoc.integration.soc_core import * # TODO: cleanup from misoc.cores.lasmicon.core import LASMIconSettings from misoc.cores.minicon.core import MiniconSettings +__all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"] + + class SDRAMCore(Module, AutoCSR): def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs): # DFI @@ -140,3 +143,7 @@ class SoCSDRAM(SoCCore): self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs, self._wb_sdram) SoCCore.do_finalize(self) + + +soc_sdram_args = soc_core_args +soc_sdram_argdict = soc_core_argdict diff --git a/misoc/targets/de0nano.py b/misoc/targets/de0nano.py index b0ca296c..2e8d80e1 100755 --- a/misoc/targets/de0nano.py +++ b/misoc/targets/de0nano.py @@ -1,9 +1,15 @@ +#!/usr/bin/env python3 + +import argparse + from migen import * +from migen.build.platforms import de0nano from misoc.cores.sdram_settings import IS42S16160 from misoc.cores.sdram_phy import GENSDRPHY from misoc.cores.lasmicon.core import LASMIconSettings -from misoc.integration.soc_sdram import SoCSDRAM +from misoc.integration.soc_sdram import * +from misoc.integration.builder import * class _PLL(Module): @@ -80,9 +86,8 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): - default_platform = "de0nano" - - def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): + def __init__(self, sdram_controller_settings=LASMIconSettings(), **kwargs): + platform = de0nano.Platform() SoCSDRAM.__init__(self, platform, clk_freq=100*1000000, integrated_rom_size=0x8000, @@ -96,4 +101,16 @@ class BaseSoC(SoCSDRAM): IS42S16160(self.clk_freq)) self.register_sdram_phy(self.sdrphy) -default_subtarget = BaseSoC +def main(): + parser = argparse.ArgumentParser(description="MiSoC port to the Altera DE0 Nano") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = BaseSoC(**soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build() + + +if __name__ == "__main__": + main() diff --git a/misoc/targets/kc705.py b/misoc/targets/kc705.py index b6278830..b58e69a3 100755 --- a/misoc/targets/kc705.py +++ b/misoc/targets/kc705.py @@ -1,5 +1,10 @@ +#!/usr/bin/env python3 + +import argparse + from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.build.platforms import kc705 from misoc.cores.sdram_settings import MT8JTF12864 from misoc.cores.sdram_phy import k7ddrphy @@ -8,7 +13,9 @@ from misoc.cores import spi_flash from misoc.cores.liteeth_mini.phy import LiteEthPHY from misoc.cores.liteeth_mini.mac import LiteEthMAC from misoc.integration.soc_core import mem_decoder -from misoc.integration.soc_sdram import SoCSDRAM +from misoc.integration.soc_sdram import * +from misoc.integration.builder import * + class _CRG(Module): @@ -77,7 +84,8 @@ class BaseSoC(SoCSDRAM): } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): + def __init__(self, toolchain="ise", sdram_controller_settings=LASMIconSettings(), **kwargs): + platform = kc705.Platform(toolchain=toolchain) SoCSDRAM.__init__(self, platform, clk_freq=125*1000000, cpu_reset_address=0xaf0000, sdram_controller_settings=sdram_controller_settings, @@ -120,12 +128,31 @@ class MiniSoC(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, platform, **kwargs): - BaseSoC.__init__(self, platform, **kwargs) + def __init__(self, *args, **kwargs): + BaseSoC.__init__(self, *args, **kwargs) - self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=self.clk_freq) + self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"), + self.platform.request("eth"), clk_freq=self.clk_freq) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) -default_subtarget = BaseSoC + +def main(): + parser = argparse.ArgumentParser(description="MiSoC port to the KC705") + builder_args(parser) + soc_sdram_args(parser) + parser.add_argument("--toolchain", default="ise", + help="FPGA toolchain to use: ise, vivado") + parser.add_argument("--with-ethernet", action="store_true", + help="enable Ethernet support") + args = parser.parse_args() + + cls = MiniSoC if args.with_ethernet else BaseSoC + soc = cls(toolchain=args.toolchain, **soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build() + + +if __name__ == "__main__": + main() diff --git a/misoc/targets/minispartan6.py b/misoc/targets/minispartan6.py index 303d3281..040ead10 100755 --- a/misoc/targets/minispartan6.py +++ b/misoc/targets/minispartan6.py @@ -1,12 +1,17 @@ +#!/usr/bin/env python3 + +import argparse from fractions import Fraction from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.build.platforms import minispartan6 from misoc.cores.sdram_settings import AS4C16M16 from misoc.cores.sdram_phy import GENSDRPHY from misoc.cores.lasmicon.core import LASMIconSettings -from misoc.integration.soc_sdram import SoCSDRAM +from misoc.integration.soc_sdram import * +from misoc.integration.builder import * class _CRG(Module): @@ -61,10 +66,9 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): - default_platform = "minispartan6" - - def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): + def __init__(self, sdram_controller_settings=LASMIconSettings(), **kwargs): clk_freq = 80*1000000 + platform = minispartan6.Platform() SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, sdram_controller_settings=sdram_controller_settings, @@ -77,4 +81,17 @@ class BaseSoC(SoCSDRAM): AS4C16M16(clk_freq)) self.register_sdram_phy(self.sdrphy) -default_subtarget = BaseSoC + +def main(): + parser = argparse.ArgumentParser(description="MiSoC port to the MiniSpartan6") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = BaseSoC(**soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build() + + +if __name__ == "__main__": + main() diff --git a/misoc/targets/mlabs_video.py b/misoc/targets/mlabs_video.py index df2d855b..8f2f8601 100755 --- a/misoc/targets/mlabs_video.py +++ b/misoc/targets/mlabs_video.py @@ -1,20 +1,25 @@ +#!/usr/bin/env python3 + +import argparse import os from fractions import Fraction from math import ceil from migen import * from migen.build.generic_platform import ConstraintError +from migen.build.platforms import mixxeo, m1 from misoc.cores.sdram_settings import MT46V32M16 from misoc.cores.sdram_phy import S6HalfRateDDRPHY from misoc.cores.lasmicon.core import LASMIconSettings from misoc.cores import nor_flash_16 -from misoc.cores import framebuffer +# TODO: from misoc.cores import framebuffer from misoc.cores import gpio from misoc.cores.liteeth_mini.phy import LiteEthPHY from misoc.cores.liteeth_mini.mac import LiteEthMAC from misoc.integration.soc_core import mem_decoder -from misoc.integration.soc_sdram import SoCSDRAM +from misoc.integration.soc_sdram import * +from misoc.integration.builder import * class _MXCRG(Module): @@ -70,9 +75,13 @@ class _MXClockPads: class BaseSoC(SoCSDRAM): - default_platform = "mixxeo" # also supports m1 - - def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): + def __init__(self, platform_name="mixxeo", sdram_controller_settings=LASMIconSettings(), **kwargs): + if platform_name == "mixxeo": + platform = mixxeo.Platform() + elif platform_name == "m1": + platform = m1.Platform() + else: + raise ValueError SoCSDRAM.__init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000000, cpu_reset_address=0x00180000, @@ -105,7 +114,7 @@ class BaseSoC(SoCSDRAM): INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2"; INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3"; """) - platform.add_source(os.path.join("misoc", "mxcrg.v")) + platform.add_source(os.path.join(misoc_directory, "cores", "mxcrg.v")) class MiniSoC(BaseSoC): @@ -125,9 +134,10 @@ class MiniSoC(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, platform, **kwargs): - BaseSoC.__init__(self, platform, **kwargs) + def __init__(self, *args, **kwargs): + BaseSoC.__init__(self, *args, **kwargs) + platform = self.platform if platform.name == "mixxeo": self.submodules.leds = gpio.GPIOOut(platform.request("user_led")) if platform.name == "m1": @@ -173,11 +183,33 @@ class FramebufferSoC(MiniSoC): } csr_map.update(MiniSoC.csr_map) - def __init__(self, platform, **kwargs): - MiniSoC.__init__(self, platform, **kwargs) + def __init__(self, *args, **kwargs): + MiniSoC.__init__(self, *args, **kwargs) pads_vga, pads_dvi = get_vga_dvi(platform) self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi, self.sdram.crossbar.get_master()) add_vga_tig(platform, self.fb) -default_subtarget = FramebufferSoC + +def main(): + parser = argparse.ArgumentParser(description="MiSoC port to the Mixxeo and Milkymist One") + builder_args(parser) + soc_sdram_args(parser) + parser.add_argument("--platform", default="mixxeo", + help="platform to build for: mixxeo, m1") + parser.add_argument("--soc-type", default="base", + help="SoC type: base, mini, framebuffer") + args = parser.parse_args() + + cls = { + "base": BaseSoC, + "mini": MiniSoC, + "framebuffer": FramebufferSoC + }[args.soc_type] + soc = cls(args.platform, **soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build() + + +if __name__ == "__main__": + main() diff --git a/misoc/targets/papilio_pro.py b/misoc/targets/papilio_pro.py index 25e003d5..f41a4d3b 100755 --- a/misoc/targets/papilio_pro.py +++ b/misoc/targets/papilio_pro.py @@ -1,5 +1,6 @@ #!/usr/bin/env python3 +import argparse from fractions import Fraction from migen import * @@ -10,8 +11,8 @@ from misoc.cores.sdram_settings import MT48LC4M16 from misoc.cores.sdram_phy import GENSDRPHY from misoc.cores.lasmicon.core import LASMIconSettings from misoc.cores import spi_flash -from misoc.integration.soc_sdram import SoCSDRAM -from misoc.integration.builder import Builder +from misoc.integration.soc_sdram import * +from misoc.integration.builder import * class _CRG(Module): @@ -71,7 +72,8 @@ class BaseSoC(SoCSDRAM): } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): + def __init__(self, sdram_controller_settings=LASMIconSettings(), **kwargs): + platform = papilio_pro.Platform() clk_freq = 80*1000000 SoCSDRAM.__init__(self, platform, clk_freq, cpu_reset_address=0x60000, @@ -93,8 +95,13 @@ class BaseSoC(SoCSDRAM): def main(): - soc = BaseSoC(papilio_pro.Platform(), cpu_type="or1k") - builder = Builder(soc, "misoc_build") + parser = argparse.ArgumentParser(description="MiSoC port to the Papilio Pro") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = BaseSoC(**soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/misoc/targets/pipistrello.py b/misoc/targets/pipistrello.py index f5a36df8..1a4f50d0 100755 --- a/misoc/targets/pipistrello.py +++ b/misoc/targets/pipistrello.py @@ -1,13 +1,18 @@ +#!/usr/bin/env python3 + +import argparse from fractions import Fraction from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.build.platforms import pipistrello from misoc.cores.sdram_settings import MT46H32M16 from misoc.cores.sdram_phy import S6HalfRateDDRPHY from misoc.cores.lasmicon.core import LASMIconSettings from misoc.cores import spi_flash -from misoc.integration.soc_sdram import SoCSDRAM +from misoc.integration.soc_sdram import * +from misoc.integration.builder import * class _CRG(Module): @@ -91,15 +96,14 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): - default_platform = "pipistrello" - csr_map = { "spiflash": 16, } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), + def __init__(self, sdram_controller_settings=LASMIconSettings(), clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs): + platform = pipistrello.Platform() SoCSDRAM.__init__(self, platform, clk_freq, cpu_reset_address=0x170000, # 1.5 MB sdram_controller_settings=sdram_controller_settings, @@ -127,4 +131,17 @@ class BaseSoC(SoCSDRAM): self.flash_boot_address = 0x180000 self.register_rom(self.spiflash.bus, 0x1000000) -default_subtarget = BaseSoC +def main(): + parser = argparse.ArgumentParser(description="MiSoC port to the Pipistrello") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = BaseSoC(**soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build() + + +if __name__ == "__main__": + main() + diff --git a/misoc/targets/simple.py b/misoc/targets/simple.py index 0c7bdc20..e6d89128 100755 --- a/misoc/targets/simple.py +++ b/misoc/targets/simple.py @@ -1,9 +1,15 @@ +#!/usr/bin/env python3 + +import argparse +import importlib + from migen import * from migen.genlib.io import CRG from misoc.cores.liteeth_mini.phy import LiteEthPHY from misoc.cores.liteeth_mini.mac import LiteEthMAC -from misoc.integration.soc_core import SoCCore, mem_decoder +from misoc.integration.soc_core import * +from misoc.integration.builder import * class BaseSoC(SoCCore): @@ -44,4 +50,24 @@ class MiniSoC(BaseSoC): self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) -default_subtarget = BaseSoC + +def main(): + parser = argparse.ArgumentParser(description="Generic MiSoC port") + builder_args(parser) + soc_core_args(parser) + parser.add_argument("--with-ethernet", action="store_true", + help="enable Ethernet support") + parser.add_argument("platform", + help="module name of the Migen platform to build for") + args = parser.parse_args() + + platform_module = importlib.import_module(args.platform) + platform = platform_module.Platform() + cls = MiniSoC if args.with_ethernet else BaseSoC + soc = cls(platform, **soc_core_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build() + + +if __name__ == "__main__": + main() diff --git a/misoc/targets/versa.py b/misoc/targets/versa.py deleted file mode 100755 index 84c7e425..00000000 --- a/misoc/targets/versa.py +++ /dev/null @@ -1,17 +0,0 @@ -from migen import * -from migen.genlib.io import CRG - -from misoc.integration.soc_core import SoCCore - - -class BaseSoC(SoCCore): - default_platform = "versa" - def __init__(self, platform, **kwargs): - SoCCore.__init__(self, platform, - clk_freq=100*1000000, - integrated_rom_size=0x8000, - **kwargs) - self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n")) - self.comb += platform.request("user_led", 0).eq(ResetSignal()) - -default_subtarget = BaseSoC