From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 1 May 2018 10:02:54 +0000 (+0200)
Subject: build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
X-Git-Tag: 24jan2021_ls180~1712
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3652935d9f0560ac32d55335b56a11199c45878;p=litex.git

build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
---

diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py
index b082c3b3..c4c1e3ba 100644
--- a/litex/build/generic_platform.py
+++ b/litex/build/generic_platform.py
@@ -3,7 +3,8 @@ import os
 from migen.fhdl.structure import Signal
 from migen.genlib.record import Record
 from migen.genlib.io import CRG
-from migen.fhdl import verilog
+
+from litex.gen.fhdl import verilog
 
 from litex.build import tools
 
diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py
index d0594ec9..e8486e33 100644
--- a/litex/build/lattice/diamond.py
+++ b/litex/build/lattice/diamond.py
@@ -7,7 +7,8 @@ import subprocess
 import shutil
 
 from migen.fhdl.structure import _Fragment
-from migen.fhdl.verilog import DummyAttrTranslate
+
+from litex.gen.fhdl.verilog import DummyAttrTranslate
 
 from litex.build.generic_platform import *
 from litex.build import tools
diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 9ed17b0e..ec858b26 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -118,17 +118,6 @@ def _printexpr(ns, node):
 def _printnode(ns, at, level, node, target_filter=None):
     if target_filter is not None and target_filter not in list_targets(node):
         return ""
-    elif isinstance(node, Display):
-        s = "\"" + node.s + "\""
-        for arg in node.args:
-            s += ", "
-            if isinstance(arg, Signal):
-                s += ns.get_name(arg)
-            else:
-                s += str(arg)
-        return "\t"*level + "$display(" + s + ");\n"
-    elif isinstance(node, Finish):
-        return "\t"*level + "$finish;\n"
     elif isinstance(node, _Assign):
         if at == _AT_BLOCKING:
             assignment = " = "