From: Richard Sandiford Date: Sun, 23 Jun 2013 20:12:53 +0000 (+0000) Subject: include/opcode/ X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3678916c694b6af469a882ae1df0dc15b89f44a;p=binutils-gdb.git include/opcode/ * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. gas/ * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 26b13eda30b..d6d9f5eac7a 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2013-06-23 Richard Sandiford + + * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments. + 2013-06-23 Richard Sandiford * config/tc-mips.c: Assert that offsetT and valueT are at least diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index e259071fa53..dba8b219d51 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -11386,8 +11386,8 @@ mips_ip (char *str, struct mips_cl_insn *ip) continue; case '3': - /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS - code) or 21 (for microMIPS code). */ + /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS + code) or 13 (for microMIPS code). */ { unsigned long mask = (mips_opts.micromips ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); @@ -11405,8 +11405,8 @@ mips_ip (char *str, struct mips_cl_insn *ip) continue; case '4': - /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS - code) or 21 (for microMIPS code). */ + /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS + code) or 12 (for microMIPS code). */ { unsigned long mask = (mips_opts.micromips ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); @@ -11424,8 +11424,8 @@ mips_ip (char *str, struct mips_cl_insn *ip) continue; case '5': - /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS - code) or 16 (for microMIPS code). */ + /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS + code) or 13 (for microMIPS code). */ { unsigned long mask = (mips_opts.micromips ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); @@ -11443,8 +11443,8 @@ mips_ip (char *str, struct mips_cl_insn *ip) continue; case '6': - /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS - code) or 21 (for microMIPS code). */ + /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS + code) or 16 (for microMIPS code). */ { unsigned long mask = (mips_opts.micromips ? MICROMIPSOP_MASK_RS : OP_MASK_RS); @@ -11461,7 +11461,9 @@ mips_ip (char *str, struct mips_cl_insn *ip) } continue; - case '7': /* Four DSP accumulators in bits 11,12. */ + case '7': + /* Four DSP accumulators in bit 11 (for standard MIPS code) + or 14 (for microMIPS code). */ if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && s[3] >= '0' && s[3] <= '3') { @@ -11509,8 +11511,8 @@ mips_ip (char *str, struct mips_cl_insn *ip) break; case '0': - /* DSP 6-bit signed immediate in bit 16 (for standard MIPS - code) or 20 (for microMIPS code). */ + /* DSP 6-bit signed immediate in bit 20 (for standard MIPS + code) or 16 (for microMIPS code). */ { long mask = (mips_opts.micromips ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 4daf47bc094..189a1d4176c 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2013-06-23 Richard Sandiford + + * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. + 2013-06-17 Catherine Moore Maciej W. Rozycki Chao-Ying Fu diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 9d241e847a6..e62ecd6e6db 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1811,7 +1811,7 @@ extern const int bfd_mips16_num_opcodes; Coprocessor instructions: "E" 5-bit target register (MICROMIPSOP_*_RT) - "G" 5-bit destination register (MICROMIPSOP_*_RD) + "G" 5-bit destination register (MICROMIPSOP_*_RS) "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) "+D" combined destination register ("G") and sel ("H") for CP0 ops, for pretty-printing in disassembly only