From: lkcl <lkcl@web>
Date: Fri, 5 May 2023 22:22:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c36965d9d392081367b972f522e4bb335a86903e;p=libreriscv.git

---

diff --git a/openpower/sv/svstep.mdwn b/openpower/sv/svstep.mdwn
index 87a3c6b48..7bb23724c 100644
--- a/openpower/sv/svstep.mdwn
+++ b/openpower/sv/svstep.mdwn
@@ -142,7 +142,9 @@ is not specifying a Sub-vector
 qualifier at all, but it is critically important to note that
 operations will be repeated.  For example if  `sv.svstep/vec2`
 is used on `sv.addi` then each Vector element operation is
-repeated twice.
+repeated twice. The reason is that whilst svstep will be
+iterating through both the SUBVL and VL loops, the addi instruction
+only uses `srcstep` and `dststep`.
 
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