From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 13 Aug 2020 12:34:36 +0000 (+0100)
Subject: sigh.  convert Fast regfile to binary
X-Git-Tag: semi_working_ecp5~378
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c36d4f307f126e40b63489d51c14f0d6143fc25b;p=soc.git

sigh.  convert Fast regfile to binary
---

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 74a955cb..81298e8e 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -97,15 +97,10 @@ def regspec_decode_read(e, regfile, name):
 
     if regfile == 'FAST':
         # FAST register numbering is *unary* encoded
-        CTR = 1<<FastRegs.CTR
-        LR = 1<<FastRegs.LR
-        TAR = 1<<FastRegs.TAR
-        SRR0 = 1<<FastRegs.SRR0
-        SRR1 = 1<<FastRegs.SRR1
         if name == 'fast1':
-            return e.read_fast1.ok, 1<<e.read_fast1.data
+            return e.read_fast1.ok, e.read_fast1.data
         if name == 'fast2':
-            return e.read_fast2.ok, 1<<e.read_fast2.data
+            return e.read_fast2.ok, e.read_fast2.data
 
     # SPR regfile
 
@@ -170,9 +165,9 @@ def regspec_decode_write(e, regfile, name):
     if regfile == 'FAST':
         # FAST register numbering is *unary* encoded
         if name == 'fast1':
-            return e.write_fast1, 1<<e.write_fast1.data
+            return e.write_fast1, e.write_fast1.data
         if name == 'fast2':
-            return e.write_fast2, 1<<e.write_fast2.data
+            return e.write_fast2, e.write_fast2.data
 
     # SPR regfile
 
diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index d088fe60..88b23209 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -75,7 +75,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
 
 
 # Fast SPRs Regfile
-class FastRegs(RegFileArray):
+class FastRegs(RegFileMem): #RegFileArray):
     """FastRegs
 
     FAST regfile  - CTR, LR, TAR, SRR1, SRR2