From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 16:59:57 +0000 (-0700)
Subject: Update doc
X-Git-Tag: working-ls180~1123^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c36fca86f7d096e64b2a0eb6a3c4f5c427c7e537;p=yosys.git

Update doc
---

diff --git a/README.md b/README.md
index 5b30f6bae..fd4d4beb5 100644
--- a/README.md
+++ b/README.md
@@ -417,9 +417,10 @@ Verilog Attributes and non-standard features
   port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths
   as a combinatorial loop.
 
-- The port attribute ``abc_carry_in`` and ``abc_carry_out`` attributes mark
-  the carry-in and carry-out ports of a box. This information is necessary for
-  `abc9` to preserve the integrity of carry-chains.
+- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
+  carry-out (if output port) ports of a box. This information is necessary for
+  `abc9` to preserve the integrity of carry-chains. Specifying this attribute
+  onto a bus port will affect its most significant bit.
 
 
 Non-standard or SystemVerilog features for formal verification