From: Luke Kenneth Casson Leighton Date: Sun, 9 Jun 2019 10:53:41 +0000 (+0100) Subject: bring in cancel array into FURegDepMatrix X-Git-Tag: div_pipeline~1865 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c37db6a8c3f7a831310982a96ee49582a3a91bec;p=soc.git bring in cancel array into FURegDepMatrix use in class which merges Partial Addr Match with FURegDepMatrix to create a MDM (Memory Dependency Matrix) --- diff --git a/src/scoreboard/addr_match.py b/src/scoreboard/addr_match.py index 6fdd055e..a042e0df 100644 --- a/src/scoreboard/addr_match.py +++ b/src/scoreboard/addr_match.py @@ -52,6 +52,9 @@ class PartialAddrMatch(Elaboratable): def elaborate(self, platform): m = Module() + return self._elaborate(m, platform) + + def _elaborate(self, m, platform): comb = m.d.comb sync = m.d.sync diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index a64ff8ce..16108229 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -27,7 +27,8 @@ class DependencyRow(Elaboratable): asynchronous) would be reset at the exact moment that GO was requested, and the RSEL would be garbage. """ - def __init__(self, n_reg, n_src): + def __init__(self, n_reg, n_src, cancel_mode=False): + self.cancel_mode = cancel_mode self.n_reg = n_reg self.n_src = n_src # arrays @@ -52,7 +53,10 @@ class DependencyRow(Elaboratable): self.go_wr_i = Signal(reset_less=True) # Go Write in (left) self.go_rd_i = Signal(reset_less=True) # Go Read in (left) - self.go_die_i = Signal(reset_less=True) # Go Die in (left) + if self.cancel_mode: + self.go_die_i = Signal(n_reg, reset_less=True) # Go Die in (left) + else: + self.go_die_i = Signal(reset_less=True) # Go Die in (left) # for Register File Select Lines (vertical) self.dest_rsel_o = Signal(n_reg, reset_less=True) # dest reg sel (bot) @@ -73,13 +77,17 @@ class DependencyRow(Elaboratable): src_c.append(src_l) # connect go_rd / go_wr (dest->wr, src->rd) - wr_die = Signal(reset_less=True) - rd_die = Signal(reset_less=True) - m.d.comb += wr_die.eq(self.go_wr_i | self.go_die_i) - m.d.comb += rd_die.eq(self.go_rd_i | self.go_die_i) - m.d.comb += dest_c.r.eq(Repl(wr_die, self.n_reg)) + wr_die = Signal(self.n_reg, reset_less=True) + rd_die = Signal(self.n_reg, reset_less=True) + if self.cancel_mode: + go_die = self.go_die_i + else: + go_die = Repl(self.go_die_i, self.n_reg) + m.d.comb += wr_die.eq(Repl(self.go_wr_i, self.n_reg) | go_die) + m.d.comb += rd_die.eq(Repl(self.go_rd_i, self.n_reg) | go_die) + m.d.comb += dest_c.r.eq(wr_die) for i in range(self.n_src): - m.d.comb += src_c[i].r.eq(Repl(rd_die, self.n_reg)) + m.d.comb += src_c[i].r.eq(rd_die) # connect input reg bit (unary) i_ext = Repl(self.issue_i, self.n_reg) @@ -150,7 +158,7 @@ def dcell_sim(dut): yield def test_dcell(): - dut = DependencyRow(4, 2) + dut = DependencyRow(4, 2, True) vl = rtlil.convert(dut, ports=dut.ports()) with open("test_drow.il", "w") as f: f.write(vl) diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py index d7f225b9..8ca1494e 100644 --- a/src/scoreboard/fu_reg_matrix.py +++ b/src/scoreboard/fu_reg_matrix.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Elaboratable, Array, Cat +from nmigen import Module, Signal, Elaboratable, Array, Cat, Repl from scoreboard.dependence_cell import DependencyRow from scoreboard.fu_wr_pending import FU_RW_Pend @@ -28,7 +28,7 @@ from scoreboard.global_pending import GlobalPending class FURegDepMatrix(Elaboratable): """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26 """ - def __init__(self, n_fu_row, n_reg_col, n_src): + def __init__(self, n_fu_row, n_reg_col, n_src, cancel=None): self.n_src = n_src self.n_fu_row = nf = n_fu_row # Y (FUs) ^v self.n_reg_col = n_reg = n_reg_col # X (Regs) <> @@ -48,6 +48,9 @@ class FURegDepMatrix(Elaboratable): self.dest_i = Signal(n_reg_col, reset_less=True) # Dest in (top) self.src_i = Array(src) # oper in (top) + # cancellation array (from Address Matching), ties in with go_die_i + self.cancel = cancel + # Register "Global" vectors for determining RaW and WaR hazards self.wr_pend_i = Signal(n_reg_col, reset_less=True) # wr pending (top) self.rd_pend_i = Signal(n_reg_col, reset_less=True) # rd pending (top) @@ -70,11 +73,15 @@ class FURegDepMatrix(Elaboratable): def elaborate(self, platform): m = Module() + return self._elaborate(m, platform) + + def _elaborate(self, m, platform): # --- # matrix of dependency cells # --- - dm = Array(DependencyRow(self.n_reg_col, self.n_src) \ + cancel_mode = self.cancel is not None + dm = Array(DependencyRow(self.n_reg_col, self.n_src, cancel_mode) \ for r in range(self.n_fu_row)) for fu in range(self.n_fu_row): setattr(m.submodules, "dr_fu%d" % fu, dm[fu]) @@ -211,22 +218,36 @@ class FURegDepMatrix(Elaboratable): # --- go_rd_i = [] go_wr_i = [] - go_die_i = [] issue_i = [] for fu in range(self.n_fu_row): dc = dm[fu] # accumulate cell fwd outputs for dest/src1/src2 go_rd_i.append(dc.go_rd_i) go_wr_i.append(dc.go_wr_i) - go_die_i.append(dc.go_die_i) issue_i.append(dc.issue_i) # wire up inputs from module to row cell inputs (Cat is gooood) m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i), Cat(*go_wr_i).eq(self.go_wr_i), - Cat(*go_die_i).eq(self.go_die_i), Cat(*issue_i).eq(self.issue_i), ] + # --- + # connect Dep go_die_i + # --- + if cancel_mode: + for fu in range(self.n_fu_row): + dc = dm[fu] + go_die = Repl(self.go_die_i[fu], self.n_fu_row) + go_die = go_die | self.cancel[fu] + m.d.comb += dc.go_die_i.eq(go_die) + else: + go_die_i = [] + for fu in range(self.n_fu_row): + dc = dm[fu] + # accumulate cell fwd outputs for dest/src1/src2 + go_die_i.append(dc.go_die_i) + # wire up inputs from module to row cell inputs (Cat is gooood) + m.d.comb += Cat(*go_die_i).eq(self.go_die_i) return m def __iter__(self): diff --git a/src/scoreboard/test_mem2_fu_matrix.py b/src/scoreboard/test_mem2_fu_matrix.py index 50659e2e..b75d2195 100644 --- a/src/scoreboard/test_mem2_fu_matrix.py +++ b/src/scoreboard/test_mem2_fu_matrix.py @@ -9,6 +9,7 @@ from scoreboard.global_pending import GlobalPending from scoreboard.group_picker import GroupPicker from scoreboard.issue_unit import IssueUnitGroup, IssueUnitArray, RegDecode from scoreboard.shadow import ShadowMatrix, BranchSpeculationRecord +from scoreboard.addr_match import PartialAddrMatch from nmutil.latch import SRLatch from nmutil.nmoperator import eq @@ -56,6 +57,21 @@ class MemSim: self.mem[addr>>self.ddepth] = data & ((1<