From: lkcl <lkcl@web>
Date: Fri, 11 Dec 2020 21:32:24 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1401
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c38064ed97a08e3de6e8a3891314b5864abcc828;p=libreriscv.git

---

diff --git a/openpower/sv/vector_swizzle.mdwn b/openpower/sv/vector_swizzle.mdwn
index 4b6688a19..6eea7a9ad 100644
--- a/openpower/sv/vector_swizzle.mdwn
+++ b/openpower/sv/vector_swizzle.mdwn
@@ -1,6 +1,7 @@
 # SV Vector Prefix Swizzle
 
-<https://bugs.libre-soc.org/show_bug.cgi?id=139>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=139>
+* <https://libre-soc.org/simple_v_extension/specification/mv.x/>
 
 3D GPU operations on batches of vec2, vec3 and vec4 often require re-ordering of the elements in an "out of lane" fashion with respect to standard high performance non-GPU-centric Vector Processors.  Examples include: