From: Oleg Endo Date: Sat, 4 Jun 2016 06:08:33 +0000 (+0000) Subject: Avoid potential slient wrong-code with reg+reg addr. modes on SH. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c389d3496ad217dbce58cc90c7cc7c7d31b40d81;p=gcc.git Avoid potential slient wrong-code with reg+reg addr. modes on SH. gcc/ * config/sh/sh.c (sh_print_operand_address): Don't use hardcoded 'r0' for reg+reg addressing mode. From-SVN: r237088 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6d3974b875e..bce140bef53 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2016-06-04 Oleg Endo + + * config/sh/sh.c (sh_print_operand_address): Don't use hardcoded 'r0' + for reg+reg addressing mode. + 2016-06-03 Bill Schmidt * rs6000-c.c (c/c-tree.h): Add #include. diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 2bd917a0940..74327aa7c7e 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -1038,8 +1038,16 @@ sh_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x) int base_num = true_regnum (base); int index_num = true_regnum (index); - fprintf (stream, "@(r0,%s)", - reg_names[MAX (base_num, index_num)]); + /* If base or index is R0, make sure that it comes first. + Usually one of them will be R0, but the order might be wrong. + If neither base nor index are R0 it's an error and we just + pass it on to the assembler. This avoids silent wrong code + bugs. */ + if (base_num == 0 && index_num != 0) + std::swap (base_num, index_num); + + fprintf (stream, "@(%s,%s)", reg_names[index_num], + reg_names[base_num]); break; }