From: lkcl <lkcl@web>
Date: Mon, 2 May 2022 10:15:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2518
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c38e2db399734b35d730214b18880cd0851d5360;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 8a591abb3..2734a7cf1 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -505,9 +505,9 @@ EXTRA is the means by which two things are achieved:
 
 The register files are therefore extended:
 
-* INT is extended from r0-31 to 128
-* FP is extended from fp0-32 to 128
-* CR is extended from CR0-7 to CR0-127
+* INT is extended from r0-31 to r0-127
+* FP is extended from fp0-32 to fp0-fp127
+* CR Fields are extended from CR0-7 to CR0-127
 
 In the following tables register numbers are constructed from the
 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2