From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 3 Nov 2018 10:26:17 +0000 (+0000)
Subject: add placeholder CSR uremap get
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3a45424ec156e538d567b8b01f122f5fecbed47;p=riscv-isa-sim.git

add placeholder CSR uremap get
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 4e15497..83e02bb 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -774,6 +774,8 @@ reg_t processor_t::get_csr(int which)
     case CSR_SVPREDCFG6:
     case CSR_SVPREDCFG7:
       return 0;// XXX TODO: return correct entry
+    case CSR_UREMAP:
+      return 0;// XXX TODO: return correct entry
 #endif
     case CSR_FFLAGS:
       require_fp;