From: Luke Kenneth Casson Leighton Date: Sun, 29 Jul 2018 09:35:26 +0000 (+0100) Subject: horrible clock-sync hack X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3add43f4187899e81e2ff205d44d8802e2c449e;p=pinmux.git horrible clock-sync hack --- diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv index 9c992fe..9fd483a 100644 --- a/src/bsv/bsv_lib/slow_peripherals_template.bsv +++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv @@ -14,6 +14,7 @@ package slow_peripherals; /*===========================*/ /*=== package imports ===*/ import Clocks::*; + import Ifc_sync:: *; import GetPut::*; import ClientServer::*; import Connectable::*; @@ -80,6 +81,7 @@ package slow_peripherals; Ifc_AxiExpansion axiexp1 <- mkAxiExpansion(); `endif Ifc_pinmux pinmux <- mkpinmux; // mandatory +{14} /*=======================================================*/ diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index ad863de..f6d11f1 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -165,8 +165,10 @@ else""" ps_ = ps + '_out' else: ps_ = ps - ret.append("mkConnection({0},\n\t\t\t{1}.{2});" - .format(ps_, n_, fname)) + cn = self._mk_actual_connection('out', name, + count, typ, + pname, ps_, n_, fname) + ret += cn fname = None if p.get('outen'): fname = self.pinname_outen(pname) @@ -174,8 +176,10 @@ else""" if isinstance(fname, str): fname = "{0}.{1}".format(n_, fname) fname = self.pinname_tweak(pname, 'outen', fname) - ret.append("mkConnection({0}_outen,\n\t\t\t{1});" - .format(ps, fname)) + cn = self._mk_actual_connection('outen', name, + count, typ, + pname, ps, n, fname) + ret += cn if typ == 'in' or typ == 'inout': fname = self.pinname_in(pname) if fname: @@ -186,11 +190,57 @@ else""" n_ = "{0}{1}".format(n, count) n_ = '{0}.{1}'.format(n_, fname) n_ = self.ifname_tweak(pname, 'in', n_) - ret.append( - "mkConnection({1},\n\t\t\t{0});".format( - ps_, n_)) + cn = self._mk_actual_connection('in', name, + count, typ, + pname, ps_, n_, fname) + ret += cn return '\n'.join(ret) + def _mk_actual_connection(self, ctype, name, count, typ, + pname, ps, n, fname): + ret = [] + if ctype == 'out': + ret.append("mkConnection({0},\n\t\t\t{1}.{2});" + .format(ps, n, fname)) + elif ctype == 'outen': + ret.append("mkConnection({0}_outen,\n\t\t\t{1});" + .format(ps, fname)) + elif ctype == 'in': + ck = self.get_clock_reset(name, count) + if ck == PBase.get_clock_reset(self, name, count): + ret.append("mkConnection({1},\n\t\t\t{0});".format( + ps, n)) + else: + n2 = "{0}{1}".format(name, count) + sync = '{0}_{1}_sync'.format(n2, pname) + ret.append("mkConnection({1}.put,\n\t\t\t{0});".format( + ps, sync)) + ret.append("mkConnection({1},\n\t\t\t{0}.get);".format( + sync, n)) + return ret + + def mk_clk_con(self, name, count): + ret = [] + ck = self.get_clock_reset(name, count) + if ck == PBase.get_clock_reset(self, name, count): + return '' + spc = "sp_clock, sp_reset" + template = """\ +Ifc_sync#({0}) {1}_sync <-mksyncconnection( + {2}, {3});""" + for p in self.peripheral.pinspecs: + typ = p['type'] + pname = p['name'] + n = name + if typ == 'in' or typ == 'inout': + #fname = self.pinname_in(pname) + n_ = "{0}{1}".format(n, count) + n_ = '{0}_{1}'.format(n_, pname) + #n_ = self.ifname_tweak(pname, 'in', n_) + ret.append(template.format("Bit#(1)", n_, spc, ck)) + return '\n'.join(ret) + + def mk_cellconn(self, *args): return '' @@ -384,6 +434,7 @@ class PeripheralIface(object): 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule', 'mkfast_peripheral', 'mk_plic', 'mk_ext_ifacedef', + 'mk_clk_con', 'mk_ext_ifacedef', 'mk_connection', 'mk_cellconn', '_mk_pincon']: fn = CallFn(self, fname) setattr(self, fname, types.MethodType(fn, self)) @@ -726,6 +777,16 @@ class PeripheralInterfaces(object): def mk_sloirqsdef(self): return " `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs) + def mk_clk_con(self): + ret = [] + for (name, count) in self.ifacecount: + for i in range(count): + if self.is_on_fastbus(name, i): + continue + txt = self.data[name].mk_clk_con(name, i) + ret.append(txt) + return '\n'.join(li(list(filter(None, ret)), 8)) + def is_on_fastbus(self, name, i): #print "fastbus mode", self.fastbusmode, name, i iname = self.data[name].iname().format(i) diff --git a/src/bsv/peripheral_gen/quart.py b/src/bsv/peripheral_gen/quart.py index 2883c33..14e0808 100644 --- a/src/bsv/peripheral_gen/quart.py +++ b/src/bsv/peripheral_gen/quart.py @@ -14,16 +14,15 @@ class quart(PBase): "method Bit#(1) %s;" % self.irq_name() def get_clock_reset(self, name, count): - return "slow_clock,slow_reset" # XXX TODO: change to uart_clock/reset + return "uart_clock,uart_reset" # XXX TODO: change to uart_clock/reset def num_axi_regs32(self): return 8 def mkslow_peripheral(self, size=0): - return "// XXX TODO: change to uart_clock/reset\n" + \ - "QUART_AXI4_Lite_Ifc quart{0} <- \n" + \ - " mkQUART(clocked_by sp_clock,\n" + \ - " reset_by sp_reset, sp_clock, sp_reset);" + return "QUART_AXI4_Lite_Ifc quart{0} <- \n" + \ + " mkQUART(clocked_by uart_clock,\n" + \ + " reset_by uart_reset, sp_clock, sp_reset);" def _mk_connection(self, name=None, count=0): return "quart{0}.slave" diff --git a/src/bsv/peripheral_gen/uart.py b/src/bsv/peripheral_gen/uart.py index 86dba41..430d798 100644 --- a/src/bsv/peripheral_gen/uart.py +++ b/src/bsv/peripheral_gen/uart.py @@ -14,10 +14,13 @@ class uart(PBase): def num_axi_regs32(self): return 8 + def get_clock_reset(self, name, count): + return "uart_clock,uart_reset" + def mkslow_peripheral(self, size=0): return "Ifc_Uart_bs uart{0} <- \n" + \ - " mkUart_bs(clocked_by sp_clock,\n" + \ - " reset_by sp_reset, sp_clock, sp_reset);" + " mkUart_bs(clocked_by uart_clock,\n" + \ + " reset_by uart_reset, sp_clock, sp_reset);" def _mk_connection(self, name=None, count=0): return "uart{0}.slave_axi_uart" diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 77300c6..0884239 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -121,6 +121,7 @@ def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells): numsloirqs = ifaces.mk_sloirqsdef() ifacedef = ifaces.mk_ext_ifacedef() ifacedef = ifaces.mk_ext_ifacedef() + clockcon = ifaces.mk_clk_con() with open(slow, "w") as bsv_file: with open(slowt) as f: @@ -129,7 +130,7 @@ def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells): fnaddrmap, mkslow, mkcon, mkcellcon, pincon, inst, mkplic, numsloirqs, ifacedef, - inst2)) + inst2, clockcon)) with open(slowmf, "w") as bsv_file: with open(slowmt) as f: