From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Sun, 1 May 2016 03:43:00 +0000 (-0700)
Subject: Initialize mtvec to DEFAULT_MTVEC
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3b19169fb150f7084edff3aad0e1d5dd2b48fc3;p=riscv-isa-sim.git

Initialize mtvec to DEFAULT_MTVEC
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ccbbd16..f4c64ac 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -115,6 +115,7 @@ void state_t::reset()
   memset(this, 0, sizeof(*this));
   prv = PRV_M;
   pc = DEFAULT_RSTVEC;
+  mtvec = DEFAULT_MTVEC;
   load_reservation = -1;
 }