From: lkcl <lkcl@web>
Date: Mon, 4 Jul 2022 09:02:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1364
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3b8d6695d872f0968a60d439d8a980d38093672;p=libreriscv.git

---

diff --git a/3d_gpu/layouts/coriolis2_180nm.mdwn b/3d_gpu/layouts/coriolis2_180nm.mdwn
index 694303e41..aa3c7d88f 100644
--- a/3d_gpu/layouts/coriolis2_180nm.mdwn
+++ b/3d_gpu/layouts/coriolis2_180nm.mdwn
@@ -73,13 +73,13 @@ to ensure complete consistency across
 JTAG also contains a Wishbone Master for direct access to Memory
 and also a DMI Interface for controlling the core.  In simulations
 a JTAG client was implemented both in nmigen HDL as well as
-verilator.  The exact same openocd scripts and direct
+verilator.  The exact same openocd scripts or direct
 JTAG connectivity using jtagremote can then be used on:
 
 * nmigen HDL simulations
 * verilator simulations
-* FPGA
-* ls180 ASIC
+* [[HDL_workflow/ECP5_FPGA]]
+* the actual ls180 ASIC
 
 [[!img 180nm_Oct2020/ls180.svg size="400x" ]]