From: lkcl <lkcl@web>
Date: Fri, 1 Jan 2021 16:28:32 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~666
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3b9ca9f327d242d698f63f4c43b6e3d8ba5eecf;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 62c7a961b..498441ff0 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -27,7 +27,16 @@ Unfortunately, even with predication added, SIMD only becomes more and
 more problematic with each power of two SIMD width increase introduced
 through an ISA revision.  The opcode proliferation, at O(N^6), inexorably
 spirals out of control in the ISA, detrimentally impacting the hardware,
-the software, the compilers and the testing and compliance.
+the software, the compilers and the testing and compliance.  Here are the typical dimensions that result in such massive proliferation:
+
+* Operation (add, mul)
+* bitwidth (8, 16, 32, 64, 128)
+* Conversion between bitwidths (FP16-FP32-64)
+* Signed/unsigned
+* HI/LO swizzle (Audio L/R channels)
+* Saturation (Clamping at max range)
+
+These typically are multiplied up to produce explicit opcodes numberingvin the thousands on, for example the ARC Video/DSP cores.
 
 Cray-style variable-length Vectors on the other hand result in
 stunningly elegant and small loops, exceptionally high data throughput