From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 May 2018 12:03:58 +0000 (+0200)
Subject: Merge pull request #551 from olofk/ice40_cells_sim_ports
X-Git-Tag: yosys-0.8~91
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3be94e967c904d4b7a0591fdaa2d86bc926ec41;p=yosys.git

Merge pull request #551 from olofk/ice40_cells_sim_ports

Avoid mixing module port declaration styles in ice40 cells_sim.v
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c3be94e967c904d4b7a0591fdaa2d86bc926ec41