From: lkcl <lkcl@web>
Date: Sat, 25 Mar 2023 23:38:09 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls001_v3~63
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3c1512d89f70544e16a9dad2b8a428fd0ff29b3;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn
index 03217387b..a0c1bfc8a 100644
--- a/openpower/sv/rfc/ls008.mdwn
+++ b/openpower/sv/rfc/ls008.mdwn
@@ -104,7 +104,7 @@ Pseudo-code:
 
 ```
     if SVi[3:4] = 0b11 then
-        # store subvl, pack and unpack in SVSTATE
+        # store pack and unpack in SVSTATE
         SVSTATE[53] <- SVi[5]
         SVSTATE[54] <- SVi[6]
         RT <- [0]*62 || SVSTATE[53:54]
@@ -133,6 +133,7 @@ SVL-Form
 
 Pseudo-code:
 
+```
     overflow <- 0b0
     VLimm <- SVi + 1
     # set or get MVL
@@ -162,10 +163,13 @@ Pseudo-code:
         # set requested Vertical-First mode, clear persist
         SVSTATE[63] <- vf
         SVSTATE[62] <- 0b0
+```
 
 Special Registers Altered:
 
+```
     CR0                     (if Rc=1)
+```
 
 -------------
 
@@ -229,10 +233,11 @@ SVSTATE contains (and permits setting of):
 * Pack - if set then srcstep/substep VL/SUBVL loop-ordering is inverted.
 * UnPack - if set then dststep/substep VL/SUBVL loop-ordering is inverted.
 * hphint - Horizontal Parallelism Hint. Indicates that
-  no Hazards exist between this number of sequentially-accessed
-   elements (including after REMAP). In Vertical First Mode
-   hardware **MUST** perform this many elements in parallel
-   per instruction. Set to zero to indicate "no hint".
+  no Hazards exist between groups of elements in sequential multiples of this number
+   (before REMAP).  By definition: elements for which `FLOOR(srcstep/hphint)` is
+   equal *before REMAP* are in the same parallelism "group". In Vertical First Mode
+   hardware **MUST ONLY** process elements in the same group, and must stop
+   Horizontal Issue at the last element of a given group. Set to zero to indicate "no hint".
 * SVme - REMAP enable bits, indicating which register is to be
    REMAPed: RA, RB, RC, RT and EA are the canonical (typical) register names
    associated with each bit, with RA being the LSB and EA being the MSB.