From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sun, 11 Dec 2016 02:04:00 +0000 (+0800)
Subject: Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
X-Git-Tag: yosys-0.8~553^2^2~18
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3c2983d12ce3b1ed6d7e025eb6b5141f3ed9b40;p=yosys.git

Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index ca3e6cdbf..1b899e8e8 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -18,7 +18,11 @@ endmodule
 module GP_ABUF(input wire IN, output wire OUT);
 	
 	assign OUT = IN;
-	
+
+	//must be 1, 5, 20, 50
+	//values >1 only available with Vdd > 2.7V
+	parameter BANDWIDTH_KHZ = 1;
+
 	//cannot simulate mixed signal IP
 	
 endmodule
@@ -412,6 +416,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 	
 endmodule
 
+module GP_PWRDET(output reg VDD_LOW);
+	initial VDD_LOW = 0;
+endmodule
+
 module GP_POR(output reg RST_DONE);
 	parameter POR_TIME = 500;