From: lkcl <lkcl@web>
Date: Sun, 8 May 2022 15:52:53 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2302
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3cb61d78773a99395e44ebd56c5e7afdf3989b4;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 9cc70584e..4afb0c392 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -173,7 +173,8 @@ candidates for further advancement are:
   (Agreements between RISC-V *Members* to not engage in patent litigation
    does nothing to stop third party patents that *legitimately pre-date*
    the newly-created RISC-V ISA)
-* MIPS, SPARC, ARC, and others, simply have no viable ecosystem.
+* MIPS, SPARC, ARC, and others, simply have no viable publicly
+  managed ecosystem. They work well within their niche markets.
 * Power ISA: protected by IBM's extensive patent portfolio for Members
   of the OpenPOWER Foundation, covered by Trademarks, permitting
   and encouraging contributions, and having software support for over