From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Sat, 23 May 2020 19:39:57 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3df0a8bc08152eac98b4bbe2e758b1196de4576;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
---

diff --git a/4d/13e48777948fc5703759273e43d60382907e9b b/4d/13e48777948fc5703759273e43d60382907e9b
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+Date: Sat, 23 May 2020 19:39:57 +0000
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+X-Bugzilla-Severity: enhancement
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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