From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 16:54:56 +0000 (-0700)
Subject: Always generate if no match
X-Git-Tag: working-ls180~1085^2~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3e9627afeb6b69f244983f2f23fb5473e61ab19;p=yosys.git

Always generate if no match
---

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index e8288c54a..bdb59c2f7 100644
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -142,7 +142,7 @@ match next
 	filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool())
 	filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool())
 	filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R)
-generate 10
+generate
 	Cell *cell = module->addCell(NEW_ID, chain.back()->type);
 	cell->setPort(\C, chain.back()->getPort(\C));
 	cell->setPort(\D, module->addWire(NEW_ID));