From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 3 Jan 2014 11:34:18 +0000 (+0100)
Subject: Another small freduce cleanup/bugfix
X-Git-Tag: yosys-0.2.0~188
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3e9f0712fa2a35cf3e4a638164aed7ab8d8ff4a;p=yosys.git

Another small freduce cleanup/bugfix
---

diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index cc3739fe4..4db11436e 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -482,7 +482,8 @@ struct FreduceWorker
 				RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
 				RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID);
 				for (auto &port : drv->connections)
-					sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
+					if (ct.cell_output(drv->type, port.first))
+						sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
 
 				if (grp[i].inverted)
 				{