From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 17 Dec 2006 16:55:24 +0000 (-0500)
Subject: Merge zizzer:/bk/newmem
X-Git-Tag: m5_2.0_beta3~271
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3ec52346b99d398916765679877686c109e3513;p=gem5.git

Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/operands.isa:
    Hand Merge

--HG--
extra : convert_revision : 4c54544e5c7a61f055ea9b00ccf5f8510df0e6c2
---

c3ec52346b99d398916765679877686c109e3513
diff --cc src/arch/sparc/isa/formats/mem/blockmem.isa
index a0b235a61,8bbbdc1da..25fffc02b
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@@ -335,5 -537,13 +537,13 @@@ def format BlockStore(code, asi, *opt_f
           decoder_output,
           exec_output,
           decode_block) = doBlockMemFormat(code, faultCode,
 -             StoreExecute, name, Name, asi, opt_flags)
 +             StoreFuncs, name, Name, asi, opt_flags)
  }};
+ 
+ def format TwinLoad(code, asi, *opt_flags) {{
+     faultCode = AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck
+     (header_output,
+      decoder_output,
+      exec_output,
+      decode_block) = doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags)
+ }};
diff --cc src/arch/sparc/isa/operands.isa
index 256f2fa43,abb82f88c..2d1c3d3b9
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@@ -56,23 -56,15 +56,26 @@@ def operands {
      # Int regs default to unsigned, but code should not count on this.
      # For clarity, descriptions that depend on unsigned behavior should
      # explicitly specify '.uq'.
 +
      'Rd': 		('IntReg', 'udw', 'RD', 'IsInteger', 1),
 +    # The Rd from the previous window
 +    'Rd_prev':		('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
 +    # The Rd from the next window
 +    'Rd_next':		('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
+     # For microcoded twin load instructions, RdTwin appears in the "code"
 -    # for the instruction and is replaced by RdLow or RdHigh by the format
++    # for the instruction is replaced by RdLow or RdHigh by the format
+     # before it's processed by the iop.
 -    'RdLow': 		('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
 -    'RdHigh':		('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
 -    'Rs1': 		('IntReg', 'udw', 'RS1', 'IsInteger', 4),
 -    'Rs2': 		('IntReg', 'udw', 'RS2', 'IsInteger', 5),
 -    'uReg0':		('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 6),
 +    # The low (even) register of a two register pair
 +    'RdLow': 		('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
 +    # The high (odd) register of a two register pair
 +    'RdHigh':		('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
 +    'Rs1': 		('IntReg', 'udw', 'RS1', 'IsInteger', 6),
 +    'Rs2': 		('IntReg', 'udw', 'RS2', 'IsInteger', 7),
 +    # A microcode register. Right now, this is the only one.
 +    'uReg0':		('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
 +    # Because double and quad precision register numbers are decoded
 +    # differently, they get different operands. The single precision versions
 +    # have an s post pended to their name.
      'Frds':		('FloatReg', 'sf', 'RD', 'IsFloating', 10),
      'Frd':		('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
      # Each Frd_N refers to the Nth double precision register from Frd.