From: Luke Kenneth Casson Leighton Date: Wed, 8 Apr 2020 14:54:09 +0000 (+0100) Subject: whoops realised src1/2 need to receive reg data, not reg # X-Git-Tag: div_pipeline~1435^2~33 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c3f89e72194fd37f122221dc6463951ef96f39a4;p=soc.git whoops realised src1/2 need to receive reg data, not reg # --- diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py index 18bbb208..13884c50 100644 --- a/src/soc/experiment/compalu.py +++ b/src/soc/experiment/compalu.py @@ -62,8 +62,8 @@ class ComputationUnitNoDelay(Elaboratable): # operation / data input self.oper_i = e.insn_type # operand self.imm_i = e.imm_data # immediate in - self.src1_i = e.read_reg1 # oper1 in - self.src2_i = e.read_reg2 # oper2 in + self.src1_i = Signal(rwid, reset_less=True) # oper1 in + self.src2_i = Signal(rwid, reset_less=True) # oper2 in self.busy_o = Signal(reset_less=True) # fn busy out self.data_o = Signal(rwid, reset_less=True) # Dest out @@ -164,8 +164,8 @@ class ComputationUnitNoDelay(Elaboratable): yield self.go_die_i yield self.oper_i yield from self.imm_i.ports() - yield from self.src1_i.ports() - yield from self.src2_i.ports() + yield self.src1_i + yield self.src2_i yield self.busy_o yield self.rd_rel_o yield self.req_rel_o