From: Irides <irides@irides.network>
Date: Thu, 16 Dec 2021 01:47:48 +0000 (-0600)
Subject: sim.pysim: use "bench" as a top level root for testbench signals.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c40b0368176c77e7d0380e405dd71caa592574f0;p=nmigen.git

sim.pysim: use "bench" as a top level root for testbench signals.

Fixes #561.
---

diff --git a/nmigen/sim/pysim.py b/nmigen/sim/pysim.py
index cc3d948..c3c40ef 100644
--- a/nmigen/sim/pysim.py
+++ b/nmigen/sim/pysim.py
@@ -19,7 +19,7 @@ class _NameExtractor:
     def __init__(self):
         self.names = SignalDict()
 
-    def __call__(self, fragment, *, hierarchy=("top",)):
+    def __call__(self, fragment, *, hierarchy=("bench", "top",)):
         def add_signal_name(signal):
             hierarchical_signal_name = (*hierarchy, signal.name)
             if signal not in self.names:
@@ -74,7 +74,7 @@ class _VCDWriter:
         trace_names = SignalDict()
         for trace in traces:
             if trace not in signal_names:
-                trace_names[trace] = {("top", trace.name)}
+                trace_names[trace] = {('bench', trace.name)}
             self.traces.append(trace)
 
         if self.vcd_writer is None:
diff --git a/tests/test_sim.py b/tests/test_sim.py
index 94b1141..7a72cca 100644
--- a/tests/test_sim.py
+++ b/tests/test_sim.py
@@ -849,7 +849,7 @@ class SimulatorRegressionTestCase(FHDLTestCase):
                 pass
         sim = Simulator(dut)
         with self.assertRaisesRegex(NameError,
-                r"^Signal 'top\.name with space_state' contains a whitespace character$"):
+                r"^Signal 'bench\.top\.name with space_state' contains a whitespace character$"):
             with open(os.path.devnull, "w") as f:
                 with sim.write_vcd(f):
                     sim.run()