From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 22 May 2018 22:46:15 +0000 (+0100)
Subject: feedback from rogier bruisse
X-Git-Tag: convert-csv-opcode-to-binary~5338
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c41dea8f41eeca82e081c6e4c5281accdf9dbca6;p=libreriscv.git

feedback from rogier bruisse
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index b05619010..49cea203f 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -119,7 +119,7 @@
   \end{itemize}
   Notes:\vspace{6pt}
    \begin{itemize}
-   \item LOAD/STORE (inc. C.LD and C.ST, LD.X: everything)
+   \item All LOAD/STORE (inc. Compressed, Int/FP versions)
    \item All ALU ops (soft / hybrid / full HW, on per-op basis)
    \item All branches become predication targets (C.FNE added)
    \item C.MV of particular interest (s/v, v/v, v/s)
@@ -303,7 +303,7 @@ for (int i = 0; i < VL; ++i)
 \end{frame}
 
 \begin{frame}[fragile]
-\frametitle{LD/LD.S/LD.X (or trap, or actual hardware loop)}
+\frametitle{VLD/VLD.S/VLD.X (or trap, or actual hardware loop)}
 
 \begin{semiverbatim}
 if (unit-strided) stride = elsize;
@@ -332,7 +332,7 @@ for (int i = 0; i < VL; ++i)
    \item vector-to-scalar (w/src-pred): VEXTRACT
    \item vector-to-vector (w/no pred): Vector Copy
    \item vector-to-vector (w/src xor dest pred): Sparse Vector Copy
-   \item vector-to-vector (w/src and dest pred): Vector Shuffle
+   \item vector-to-vector (w/src and dest pred): Vector Gather/Scatter
   \end{itemize}
   \vspace{8pt}
   Notes:\vspace{10pt}