From: Andrew Waterman <aswaterman@gmail.com>
Date: Sat, 3 Jan 2015 07:17:44 +0000 (-0800)
Subject: Require 4-byte instruction alignment until RVC is reimplemented
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c42146fbe46827af81fde8542212dc3c6e69aa57;p=riscv-isa-sim.git

Require 4-byte instruction alignment until RVC is reimplemented
---

diff --git a/riscv/mmu.h b/riscv/mmu.h
index d24ed18..329f291 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -89,7 +89,8 @@ public:
     if (likely(entry->tag == addr))
       return entry;
 
-    char* iaddr = (char*)translate(addr, 2, false, true);
+    bool rvc = false; // set this dynamically once RVC is re-implemented
+    char* iaddr = (char*)translate(addr, rvc ? 2 : 4, false, true);
     insn_bits_t insn = *(uint16_t*)iaddr;
 
     if (unlikely(insn_length(insn) == 2)) {