From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 3 Dec 2021 19:35:41 +0000 (+0000)
Subject: priv_mode/virt_mode are set in the request, which is passed through
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4241ff0fcbf0a29a3c02f5de53df88b2dc658db;p=soc.git

priv_mode/virt_mode are set in the request, which is passed through
to the MMU, via the PortInterface "pr" parameter.

MMU should not itself be attempting to set d_in.priv_mode/virt_mode

this fixes case_5_ldst_exception
---

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index d3c91fdb..09f5c487 100644
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -327,9 +327,8 @@ class LoadStore1(PortInterfaceBase):
             m.d.comb += d_out.byte_sel.eq(self.req.byte_sel)
             m.d.comb += self.addr.eq(self.req.addr)
             m.d.comb += d_out.nc.eq(self.req.nc)
-            # XXX driver conflict.  ehn??
-            # XXX m.d.comb += d_out.priv_mode.eq(self.req.priv_mode)
-            # XXX m.d.comb += d_out.virt_mode.eq(self.req.virt_mode)
+            m.d.comb += d_out.priv_mode.eq(self.req.priv_mode)
+            m.d.comb += d_out.virt_mode.eq(self.req.virt_mode)
             #m.d.comb += Display("validblip dcbz=%i addr=%x",
             #self.req.dcbz,self.req.addr)
             m.d.comb += d_out.dcbz.eq(self.req.dcbz)
@@ -338,9 +337,8 @@ class LoadStore1(PortInterfaceBase):
             m.d.comb += d_out.byte_sel.eq(ldst_r.byte_sel)
             m.d.comb += self.addr.eq(ldst_r.addr)
             m.d.comb += d_out.nc.eq(ldst_r.nc)
-            # XXX driver conflict.  ehn??
-            # XXX m.d.comb += d_out.priv_mode.eq(ldst_r.priv_mode)
-            # XXX m.d.comb += d_out.virt_mode.eq(ldst_r.virt_mode)
+            m.d.comb += d_out.priv_mode.eq(ldst_r.priv_mode)
+            m.d.comb += d_out.virt_mode.eq(ldst_r.virt_mode)
             #m.d.comb += Display("no_validblip dcbz=%i addr=%x",
             #ldst_r.dcbz,ldst_r.addr)
             m.d.comb += d_out.dcbz.eq(ldst_r.dcbz)
diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index f09fd987..373f2cc8 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -108,8 +108,10 @@ class FSMMMUStage(ControlBase):
         comb += spr.eq(decode_spr_num(x_fields.SPR))
 
         # based on MSR bits, set priv and virt mode.  TODO: 32-bit mode
-        comb += d_in.priv_mode.eq(~msr_i[MSR.PR])
-        comb += d_in.virt_mode.eq(msr_i[MSR.DR])
+        # XXX WARK-WARK, this should be done in loadstore.py
+        # (through the PortInterface)
+        #comb += d_in.priv_mode.eq(~msr_i[MSR.PR])
+        #comb += d_in.virt_mode.eq(msr_i[MSR.DR])
         #comb += d_in.mode_32bit.eq(msr_i[MSR.SF]) # ?? err
 
         # ok so we have to "pulse" the MMU (or dcache) rather than