From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 11 Feb 2017 10:47:51 +0000 (+0100)
Subject: Fix another stupid bug in the same line
X-Git-Tag: yosys-0.8~499
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c449f4b86f66ca4ef2396454f09a73d56ff06512;p=yosys.git

Fix another stupid bug in the same line
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 9af4ce047..cde72a8e3 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -824,7 +824,7 @@ struct VerificImporter
 
 				SigBit outsig = net_map.at(out);
 				log_assert(outsig.wire && GetSize(outsig.wire) == 1);
-				outsig.wire->attributes["\\init"] = Const(0, 1);
+				outsig.wire->attributes["\\init"] = Const(1, 1);
 
 				module->addDff(NEW_ID, net_map.at(clk), net_map.at(in2), net_map.at(out));
 				continue;