From: Jacob Lifshay Date: Fri, 8 Jul 2022 06:14:32 +0000 (-0700) Subject: fix code block rendering X-Git-Tag: opf_rfc_ls005_v1~1274 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c454c8adb0f7b267abec2a56c898d0bee491b2fb;p=libreriscv.git fix code block rendering --- diff --git a/openpower/atomics.mdwn b/openpower/atomics.mdwn index cde1ff525..79ee04f26 100644 --- a/openpower/atomics.mdwn +++ b/openpower/atomics.mdwn @@ -12,6 +12,7 @@ Implementations have a hard time recognizing existing atomic operations via macr There is also the issue that PowerISA's memory fences are unnecessarily strong, particularly `isync` which is used for a lot of `acquire` and stronger fences. `isync` forces the cpu to do a full pipeline flush, which is unnecessary when all that is needed is a memory barrier. `atomic_fetch_add_seq_cst` is 6 instructions including a loop: + ``` # address in r4, addend in r5 sync @@ -25,6 +26,7 @@ loop: ``` `atomic_load_seq_cst` is 5 instructions, including a branch, and an unnecessarily-strong memory fence: + ``` # address in r3 sync @@ -37,6 +39,7 @@ skip: ``` `atomic_compare_exchange_strong_seq_cst` is 7 instructions, including a loop with 2 branches, and an unnecessarily-strong memory fence: + ``` # address in r4, compared-to value in r5, replacement value in r6 sync @@ -52,6 +55,7 @@ not_eq: ``` `atomic_load_acquire` is 4 instructions, including a branch and an unnecessarily-strong memory fence: + ``` ld 3, 0(3) cmpw 0, 3, 3